K4C561638C-TCD4000 Datasheet, PDF (36/42 Pages) Samsung semiconductor – 256Mb Network-DRAM

K4C5608/1638C
256Mb Network-DRAM
Function Description
Network-DRAM
The Network-DRAM is Double Data Rate (DDR) operating. The Network-DRAM is competent to perform fast random core access,
low latency, low consumption and high-speed data bandwidth.
Pin Functions
Clock Inputs : CK & CK
The CK and CK inputs are used as the reference for synchronus operation. CK is master clock input. The CS, FN and all address
input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK. The DQS and DQ and DQ output
data are referenced to the crossing point of CK and CK. The timing reference point for the differential clock is when the CK and CK sig-
nals cross during a transition.
Power Down : PD
The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a Clock Suspend function like
a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into low state if any Read or Write operation is being per-
formed.
Chip Select & Function Control : CS & FN
The CS and FN inputs are a control aignal for forming the operation commands on Network-DRAM. Each operation mode is decided
by the combination of the two consecutive operation commands using the CS and FN inputs.
Bank Addresses : BA0 & BA1
The BA0 and BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected the bank to be used for
the operation.
BA0
BA1
Bank #0
0
0
Bank #1
1
0
Bank #2
0
1
Bank #3
1
1
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REV. 0.7 Aug. 2003