K4C561638C-TCD4000 Datasheet, PDF (25/42 Pages) Samsung semiconductor – 256Mb Network-DRAM

K4C5608/1638C
Timing Diagrams
Single Bank Read Timing (CL = 3)
0
1
2
3
4
CK
CK
I_RC = 5 cycles
Command
RDA LAL
DESL
256Mb Network-DRAM
5
6
7
8
9
10
11
I_RC = 5 cycles
RDA LAL
DESL
RDA LAL
BL = 2
DQS
(Output)
I_RCD = 1 cycle
Hi-Z
DQ
Hi-Z
(Output)
BL = 4
DQS
Hi-Z
(Output)
DQ
Hi-Z
(Output)
I_RAS = 4 cycles
CL = 3
CL = 3
I_RCD = 1 cycle
I_RAS = 4 cycles
Hi-Z
Q0 Q1
CL = 3
Hi-Z
Q0 Q1 Q2 Q3
Hi-Z
CL = 3
Hi-Z
Single Bank Read Timing (CL = 4)
0
1
2
3
4
5
6
7
8
CK
CK
I_RC = 5 cycles
I_RC = 5 cycles
Command
RDA LAL
DESL
RDA LAL
DESL
Hi-Z
Q0 Q1
Hi-Z
Hi-Z
Q0 Q1 Q2 Q3 ^Hi-Z
9
10
11
RDA LAL
BL = 2
DQS
(Output)
I_RCD = 1 cycle
Hi-Z
DQ
Hi-Z
(Output)
BL = 4
DQS
Hi-Z
(Output)
DQ
Hi-Z
(Output)
I_RAS = 4 cycles
CL = 4
CL = 4
I_RCD = 1 cycle
I_RAS = 4 cycles
Hi-Z
Q0 Q1
Hi-Z
CL = 4
Q0 Q1 Q2 Q3
Hi-Z
CL = 4
Hi-Z
Q0 Q1
Q0 Q1 Q2
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REV. 0.7 Aug. 2003