K4C561638C-TCD4000 Datasheet, PDF (30/42 Pages) Samsung semiconductor – 256Mb Network-DRAM

K4C5608/1638C
256Mb Network-DRAM
Multiple Bank Read-Write Timing (BL = 2)
0
1
2
3
4
5
6
7
8
9
10
11
CK
CK
Command
I_RBD = 2 cycles I_RCD = 1 cycle
I_RWD = 2 cycles
I_RBD = 2 cycles
WRAa LALa RDAb LALb DESL WRAc LALc
I_RC = 5 cycles
I_RWD = 2 cycles
RDAd LALd DESL WRAc
LALc
I_RCD = 1 cycle I_WRD = 1 cycle
Bank Add.
(BA0, BA1)
Bank"a"
X Bank"b"
X
CL = 3
t_DQSS
Hi-Z
DQS
I_RCD = 1 cycle I_WRD = 1 cycle
Bank"c" X Bank"d"
X
t_DQSS
Hi-Z
I_RCD = 1 cycle
Bank"c" X
Hi-Z
Hi-Z
DQ
CL = 4
Hi-Z
DQS
Hi-Z
DQ
WL = 2
Da0 Da1
t_DQSS
CL = 3
WL = 2
Qb0 Qb1
Hi-Z
Dc0 Dc1
t_DQSS
CL = 3
Qd0
Hi-Z
WL =3
CL = 4
Hi-Z
Da0 Da1
WL = 3
Qb0 Qb1
Dc0 Dc1
CL = 4
Hi-Z
Multiple Bank Read-Write Timing (BL = 4)
0
1
2
3
4
5
CK
CK
Command
I_RBD = 2 cycles I_RCD = 1 cycle
WRAa LALa RDAb LALb
I_RWD = 3 cycles
DESL
I_RCD = 1 cycle I_WRD = 1 cycle
Bank Add.
(BA0, BA1)
Bank"a"
X Bank"b"
X
CL = 3
t_DQSS
Hi-Z
DQS
6
7
8
9
I_RBD = 2 cycles
I_RCD = 1 cycle
WRAc LALc RDAd LALd
I_RCD = 1 cycle I_WRD = 1 cycle
Bank"c" X Bank"d"
t_DQSS
10
11
DESL
X
Hi-Z
DQ
CL = 4
Hi-Z
DQS
Hi-Z
DQ
WL = 2
CL = 3
Hi-Z
Da0 Da1 Da2 Da3
t_DQSS
WL = 2
Qb0 Qb1 Qb2 Qb3
CL = 3
Hi-Z
Dc0 Dc1 Dc2 Dc3
t_DQSS
WL = 3
CL = 4
Da0 Da1 Da2 Da3
WL = 3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Note : "X" is dont care
I_RC to the same bank must be satisfied.
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REV. 0.7 Aug. 2003