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K4C561638C-TCD4000 Datasheet, PDF (11/42 Pages) Samsung semiconductor – 256Mb Network-DRAM
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K4C5608/1638C
256Mb Network-DRAM
AC Characteristics and Operating Conditions (Notes : 1, 2)
Symbol
Item
D4(400Mbps)
Min
Max
DA(366Mbps)
Min
Max
D3(333Mbps)
Min
Max
Units Notes
tRC
Random Cycle Time
25
-
27.5
-
30
-
3
tCK
Clock Cycle Time
CL = 3
5.5
7.5
6
7.5
6.5
7.5
3
CL = 4
5
7.5
5.5
7.5
6
7.5
3
tRAC
Random Access Time
-
22
-
24
-
26
3
tCH
Clock High Time
0.45*tCK
-
0.45*tCK
-
0.45*tCK
-
3
tCL
Clock Low Time
0.45*tCK
-
0.45*tCK
-
0.45*tCK
-
3
tCKQS DQS Access Time from CLK
-0.65
0.65
-0.75
0.75
-0.85
0.85
3, 8
tQSQ
Data Output Skew from DQS
-
0.4
-
0.45
-
0.5
4
tAC
Data Access Time from CLK
-0.65
0.65
-0.75
0.75
-0.85
0.85
3, 8
tOH
Data Output Hold Time from CLK
-0.65
0.65
-0.75
0.75
-0.85
0.85
3, 8
tQSPRE DQS(Read) Preamble Pulse Width
0.9*tCK-0.2 1.1*tCK+0.2 0.9*tCK-0.2 1.1*tCK+0.2 0.9*tCK-0.2 1.1*tCK+0.2
3
tHP
CLK half period ( minium of Actual tCH, tCL)
min(tCH, tCL)
-
min(tCH, tCL)
-
min(tCH, tCL)
-
tQSP
DQS(Read) Pulse Width
tHP-0.55
-
tHP-0.6
-
tHP-0.65
-
4
tQSQV Data Output Valid Time from DQS
tHP-0.55
-
tHP-0.6
tHP-0.65
-
4
tDQSS DQS(Write) Low to High Setup Time
0.75*tCK
1.25*tCK
0.75*tCK
1.25*tCK
0.75*tCK
1.25*tCK
3
tDSPRE DQS(Write) Preamble Pulse Width
0.4*tCK
-
0.4*tCK
-
0.4*tCK
-
4
tDSPRES DQS First Input Setup Time
0
-
0
-
0
-
3
tDSPREH DQS First Low Input Hold Time
0.25*tCK
-
0.25*tCK
-
0.25*tCK
-
3
tDSP
tDSS
DQS High or Low Input Pulse Width
DQS Input Falling Edge to Clock Setup Time
0.45*tCK
0.55*tCK
0.45*tCK
0.55*tCK
0.45*tCK
0.55*tCK
4
CL = 3
1.3
-
1.4
-
1.5
-
ns
3, 4
CL = 4
1.3
-
1.4
-
1.5
-
3, 4
tDSPST DQS(Write) Postamble Pulse Width
0.45*tCK
-
0.45*tCK
0.45*tCK
-
4
CL = 3
1.3
-
1.4
-
1.5
-
3, 4
tDSPSTH DQS(Write) Postamble Hold Time
CL = 4
1.3
-
1.4
-
1.5
-
3, 4
tDSSK UDQS - LDQS Skew (x16)
-0.5*tCK
0.5*tCK
-0.5*tCK
0.5*tCK
-0.5*tCK
0.5*tCK
tDS
Data Input Setup Time from DQS
0.5
-
0.5
-
0.6
-
4
tDH
Data Input Hold Time from DQS
0.5
-
0.5
-
0.6
-
4
tDIPW Data Input pulse Width (for each device)
1.5
-
1.5
-
1.9
-
tIS
Command / Address Input Setup Time
0.9
-
0.9
-
1
-
3
tIH
Command / Address Input Hold Time
0.9
-
0.9
-
1
-
3
tIPW
Command / Address Input Pulse Width (for each device)
2.0
-
2.0
-
2.2
-
tLZ
Data-out Low Impedance Time from CLK
-0.65
-
-0.75
-
-0.85
-
3, 6, 8
tHZ
Data-out High Impedance Time from CLK
-
0.65
-
0.75
-
0.85
3, 7, 8
tQSLZ DQS-out Low Impedance Time from CLK
-0.65
-
-0.75
-
-0.85
-
3, 6, 8
tQSHZ DQS-out High Impedance Time from CLK
-0.65
0.65
-0.75
0.75
-0.85
0.85
3, 7, 8
tQPDH Last Output to PD High Hold Time
0
-
0
-
0
-
tPDEX Power Down Exit Time
2
-
2
-
2
-
3
tT
Input Transition Time
0.1
1
0.1
1
0.1
1
tFPDL PD Low Input Window for Self-Refresh Entry
-0.5*tCK
5
-0.5*tCK
5
-0.5*tCK
5
3
- 11 -
REV. 0.7 Aug. 2003
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