K4C561638C-TCD4000 Datasheet, PDF (32/42 Pages) Samsung semiconductor – 256Mb Network-DRAM

K4C5608/1638C
256Mb Network-DRAM
Mode Register Set Timing (CL=3, BL=2)
0
1
2
3
4
CK
CK
I_RC = 5 cycles
Command
RDA LAL
DESL
A14 to A0
BA0, BA1
I_RCD = 1 cycle
BA,UA LA
I_RAS = 4 cycles
X
5
6
7
RDA MRS
I_RCD = 1 cycle
Valid
(Op-Code)
DQS
Hi-Z
(Output)
DQ
Hi-Z
(Output)
CL = 3
Hi-Z
Q0 Q1
Hi-Z
8
9
10
11
I_RCS = 5 cycles
DESL
X
RDA
or
WRA
BA,UA
Power Down Timing (CL=3, BL=2)
0
1
2
3
4
5
6
7
CK
CK
Command
A14 to A0
BA0, BA1
RDA LAL
I_RCD = 1 cycle
DQS
Hi-Z
(Output)
DQ
Hi-Z
(Output)
CL = 3
DESL
t_IH t_IS IPD = 1 cycle
t_QPDH
Hi-Z
Q0 Q1
Hi-Z
n-1
n
n+1
n+2
I_PDA = 1 cycles
X
DESL
RDA
or
WRA
t_PDEX
Power Down Entry
Power Down Exit
Note : "x" is don’t care.
IPD is defined from the first clock rising edage after PD is brought to "Low".
IPDA is defined from the first clock rising edage after PD is brought to "High".
PD must be kept "High" level until end of Burst data output.
PD should be brought to high within t_REFI(max) to maintain the data written into cell.
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REV. 0.7 Aug. 2003