K4C561638C-TCD4000 Datasheet, PDF (29/42 Pages) Samsung semiconductor – 256Mb Network-DRAM

K4C5608/1638C
256Mb Network-DRAM
Multiple Bank Write Timing (CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
CK
CK
I_RC = 5 cycles
I_RBD = 2 cycles I_RCD = 1 cycle
I_RCD = 1 cycle
Command
Bank Add.
(BA0, BA1)
BL = 2
DQS
(input)
DQ
(input)
BL = 4
DQS
(input)
WRAa LALa
I_RCD = 1 cycle
WRAb LALb
I_RAS = 4 cycles
DESL
WRAa LALa
I_RCD = 1 cycle
WRAc LALc WRAd LALd WRAb
I_RBD = 2 cycles
I_RBD = 2 cycles
Bank"a" X Bank"b"
I_RBD = 2 cycles
X
Bank"a"
t_DQSS
X Bank"c"
X Bank"d"
X Bank"b"
WL = 2
Da0 Da1
t_DQSS
Db0 Db1
t_DQSS
t_DQSS
WL = 2
Da0 Da1
t_DQSS
Dc0 Dc1
WL = 2
WL = 2
DQ
(input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Dc0 Dc1 Dc2
Multiple Bank Write Timing (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
CK
CK
I_RC = 5 cycles
I_RBD = 2 cycles I_RCD = 1 cycle
I_RCD = 1 cycle
Command
Bank Add.
(BA0, BA1)
BL = 2
DQS
(input)
DQ
(input)
BL = 4
DQS
(input)
WRAa LALa
I_RCD = 1 cycle
WRAb LALb
I_RAS = 4 cycles
DESL
WRAa LALa
I_RCD = 1 cycle
WRAc LALc WRAd LALd WRAb
I_RBD = 2 cycles
I_RBD = 2 cycles
Bank"a" X Bank"b"
I_RBD = 2 cycles
X
Bank"a" X Bank"c" X Bank"d" X Bank"b"
t_DQSS
WL = 3
Da0 Da1
t_DQSS
Db0 Db1
t_DQSS
WL = 3
t_DQSS
Da0 Da1
t_DQSS
Dc0 Dc1
WL = 3
WL = 3
DQ
(input)
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Da0 Da1 Da2 Da3 Dc0 Dc1
Note :
means "H" or "L" "X" is don’t care I_RC to the same bank must be satisfied.
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REV. 0.7 Aug. 2003