M16C6KA_15 Datasheet, PDF (99/270 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description

M16C/6KA Group
Clock synchronous serial I/O mode
• Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
“1”
Transmit enable
bit (TE)
“0”
Transmit buffer ^{“1”}
empty flag (Tl)
“0”
“H”
CTS1
“L”
CLK1
Data is set in UART1 transmit buffer register
Transferred from UART1 transmit buffer register to UART1 transmit register
TCLK
Stopped because CTS = “H”
Stopped because transfer enable bit = “0”
TxD1
Transmit
“1”
register empty
flag (TXEPT)
“0”
Transmit interrupt ^{“1”}
request bit (IR) “0”
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Shown in ( ) are bit symbols.
Cleared to “0” when interrupt request is accepted, or cleared by software
The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
• CLK polarity selection bit = “0”.
• Transmit interrupt factor selection bit = “0”.
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRG1 count source (f1, f8, f32)
n: value set to BRG1
• Example of receive timing (when external clock is selected)
“1”
Receive enable
bit (RE)
“0”
“1”
Transmit enable
bit (TE)
“0”
Transmit buffer ^{“1”}
empty flag (Tl) “0”
“H”
RTS1
“L”
Dummy data is set in UART1 transmit buffer register
Transferred from UART1 transmit buffer register to UART1 transmit register
1 / fEXT
CLK1
Receive data is taken in
RxD1
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5
Transferred from UART1 receive register
Receive complete ^{“1”}
to UART1 receive buffer register
flag (Rl)
“0”
Read out from UART1 receive buffer register
Receive interrupt ^{“1”}
request bit (IR) “0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• External clock is selected.
• RTS function is selected.
• CLK polarity selection bit = “0”.
fEXT: frequency of external clock
The following conditions should be matched when the input level of
CLK1 pin is "H" before the data reception.
• Transmit enable bit “1”
• Receive enable bit “1”
• Dummy data write to UART1 transmit buffer register
Fig.GA-9 Typical transmit/receive timings in clock synchronous serial I/O mode
Rev.1.00 Jul 16, 2004 page 97 of 266
REJ03B0100-0100Z