M16C6KA_15 Datasheet, PDF (67/270 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description

M16C/6KA Group
Watchdog Timer
Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is
a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog
timer interrupt is generated when an underflow occurs in the watchdog timer. Bit 7 of the watchdog timer
control register (address 000F16) selects the prescaler division ratio (by 16 or by 128). Thus the watchdog
timer's period can be calculated as given below. The watchdog timer's period is, however, subject to an error
due to the prescaler.
With XIN chosen for BCLK
Watchdog timer period =
prescaler dividing ratio (16 or 128) X watchdog timer count (32768)
BCLK
For example, suppose that BCLK runs at 16 MHz and that 16 has been chosen for the dividing ratio of the
prescaler, then the watchdog timer's period becomes approximately 32.7 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a
watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16).
Fig.DG-1 shows the block diagram of the watchdog timer. Fig.DG-2 shows the watchdog timer-related reg-
isters.
BCLK
HOLD
Write to the watchdog timer
start register
(address 000E16)
RESET
Prescaler
“WDC7 = 0”
1/16
“WDC7 = 1”
1/128
Watchdog timer
Set to
“7FFF16”
Watchdog timer
interrupt request
Fig.DG-1 Block diagram of watchdog timer
Rev.1.00 Jul 16, 2004 page 65 of 266
REJ03B0100-0100Z