M16C6KA_15 Datasheet, PDF (240/270 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description

M16C/6KA Group
CPU Reprogram Mode
Feature Outline (CPU reprogram mode)
In CPU reprogram mode, the writing and reading of the commands and data should be in even address ("0"
for byte address A0) in 16-bit unit, so the 8-bit unit S/W commands should be written in even address.
Commands are ignored with odd address.
Fig.BB-1 shows the flash recognition register, the flash control register 0 and the flash control register 1.
Bit 0 of flash control register 0 is the RY/BY status flag exclusively used to read the operating status of the
flash memory. During programming and erasing operation, it is "0", otherwise it is "1".
Bit 1 of flash control register 0 is EW0 mode selection bit. When setting the bit to "1", EW0 mode is selected
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and the receiving of software command is possible. Keep NMI pin to "H" for the setting. For setting the bit to
"1", it is necessary to set the bit to "0" and then to "1" in secession. For setting "0", only set the bit to "0".
Bit 3 of flash control register 0 is the flash memory reset bit used to reset the control circuit of the on-chip
flash memory. The bit is used when exiting EW0 mode and when flash memory access has failed. When
EW0 mode selection bit is "1", writing "1" to the bit resets the control circuit.
Bit 5 of the flash control register 0 is the user ROM selection bit. It is enabled only in boot mode. When the bit
is set to "1", the accessed area is switched from boot ROM to user ROM. When CPU reprogram mode is
entered in boot mode, set this bit to "1". The bit is disabled when program starts in user ROM. When in boot
mode, the function of the bit is enabled regardless the CPU rewrite mode. Write the bit with the program that
is not located in on-chip flash memory area.
Bit 6 of the flash control register 0 is a read only bit indicating the status of auto program operation. The bit is
set to "1" when a program error occurs. Otherwise, it is cleared to "0".
Bit 7 of the flash control register 0 is a read only bit indicating the status of auto erase operation. The bit is set
to "1" when a erase error occurs. Otherwise, it is cleared to "0".
Fig. BB-2 and Fig. BB-3 show the flow charts of the setting/resetting for EW0 mode and EW1 mode respectively.
The operation specified in the flow chart should be followed.
Bit 1 of flash control register 1 is EW1 mode selection bit. When setting the bit to "1", EW1 mode is selected
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and the receiving of software command is possible. Keep NMI pin to "H" for the setting. For setting the bit to
"1", the EW0 mode selection bit should be "1" and it is necessary to set the bit to "0" and then to "1" in
succession. For setting to "0", only set the bit to "0". In the case that EW1 selection bit is set to "1" (both EW0
and EW1 mode selection bits are set to "1"), if writing "0" to EW0 mode selection bit, both EW0 and EW1
mode selection bits are cleared to "0".
Rev.1.00 Jul 16, 2004 page 238 of 266
REJ03B0100-0100Z