M16C6KA_15 Datasheet, PDF (48/270 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description

M16C/6KA Group
Interrupt
Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selection
bits and processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated
by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bits are located
in the interrupt control register of each interrupt. The interrupt enable flag (I flag) and the IPL are located in
the flag register (FLG).
Fig.DD-3 and DD-4 shows the memory map of the interrupt control registers.
Interrupt control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
LRSTIC
ADIC
IBFiIC(i=0 to 3)
TAiIC(i=0 to 4)
TBiIC(i=0 to 5)
OBEIC
PS2iIC(i=0 to 2)
S1RIC
S1TIC
KUPiIC(i=0,1)
SiIC(i=3,4)
IICiIC(i=0 to 2)
SCLDAiIC(i=0 to 2)
Address
004116
004416
004516 to 004816
004A16 to 004E16
004F16 to 005416
005516
005616 to 005816
005B16
005C16
005F16,006016
006116,006216
006316,006516,006716
006416,006616,006816
When reset
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
Bit symbol
ILVL0
Bit name
Interrupt priority level
select bit
ILVL1
ILVL2
Function
RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
IR
Interrupt request bit
Nothing is assigned.
0 : Interrupt not requested
1 : Interrupt requested
(Note 1)
Note 1: Can only be writing by “0” (Please do not write “1” to this bit)
Fig.DD-3 Interrupt control registers(1)
Rev.1.00 Jul 16, 2004 page 46 of 266
REJ03B0100-0100Z