M16C6KA_15 Datasheet, PDF (37/270 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description

M16C/6KA Group
Status Transition Of BCLK
Status Transition Of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table.WA-4 shows the operating modes corresponding to the settings of system clock control regis-
ters 0 and 1.
After a reset, operation defaults to division by 8 mode. When shifting from high speed mode or mid-speed
mode to stop mode, and after a reset main clock division select bit 0 (bit 6 at address 000616) is set to “1”.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. After reset, it works in this mode. Note that oscillation of
the main clock must have stabilized before transferring from this mode to No-division, Division by 2 and
Division by 4 mode.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is used as the BCLK.
Table.WA-4 Operating modes dictated by settings of system clock control registers 0 and 1
CM17 CM16
CM06
Operating mode of BCLK
0
1
0
Division by 2 mode
1
0
0
Division by 4 mode
Invalid Invalid
1
Division by 8 mode
1
1
0
Division by 16 mode
0
0
0
No-division mode
Rev.1.00 Jul 16, 2004 page 35 of 266
REJ03B0100-0100Z