M16C6KA_15 Datasheet, PDF (169/270 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description

M16C/6KA Group
MULTI-MASTER I²C-BUS Interface
I²C0, I²C1 control register 1
I²C control register 10, 11, 12 (address 032616, 033616, 031616) controls I²C-BUS interface circuit.
•Bit 0 : Interrupt enable bit by STOP condition (SIM )
It is possible for I²C-BUS interface to request an interrupt by detecting a STOP condition. If the bit set to “1”,
an interrupt from I²C-BUS interface occurs by detecting a STOP condition ( There is no change for PIN flag)
•Bit 1: Interrupt enable bit at the completion of data receiving (WIT)
When with-ACK mode (ACK bit = “1”) is specified, by enabling the interrupt at the completion of data
receiving (WIT bit = “1”), the I²C interrupt request occurs and PIN bit becomes “0” synchronized with the
falling edge of last data bit clock. SCL is fixed “L” and the generation of ACK clock is suppressed.
Table GC-3 and Fig.GC-10 show the I²C interrupt request timing and the method of communication restart.
After the communication restart, synchronized with the falling edge of ACK clock, PIN bit becomes to “0”
and I²C interrupt request occurs.
Table.GC-3 Timing of interrupt generation in data receiving
The timing of I²C interrupt generation
(1) Synchronized with the falling edge of the
last data bit clock
The method of communication restart
The execution of writing to ACKBIT of I²C clock control
register. (Do not write to I²C data shift register.
The processing of ACK clock would be incorrect.)
(2) Synchronized with the falling edge of the The execution of writing to I²C data shift register
ACK clock
The state of internal WAIT flag can be read out by reading the WIT bit. The internal WAIT flag is set after
writing to I²C data shift register, and it is reset after writing to I²C clock control register. Consequently, which
of the timing 1) and 2) of interrupt request occurring can be understood. (See Fig.GC-10)In the cases of
transmission and address data reception immediately after the START condition, the interrupt request only
occurs at the falling edge of ACK clock regardless of the value of WIT bit and the WAIT flag remains the reset
state. Write “0” to WIT bit when in NACK is specified. (ACK bit = “0”)
Rev.1.00 Jul 16, 2004 page 167 of 266
REJ03B0100-0100Z