M16C6KA_15 Datasheet, PDF (60/270 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description

M16C/6KA Group
Interrupt
Key Input Interrupt 1
If any of the bits of key input interrupt 1 enable register (Address: 02F416) are set to “1”, the key input
interrupt 1 request occurs when a falling or a rising edge is input to one of the corresponding pins.
The effective input edge of key input interrupt 1 is determined by the edge selection bit of key input
interrupt 1 edge selection register (Address: 02F516). When the bit is set to “0”, at the falling edge,
when the bit is set to “1”, at the rising edge of the input signal to the corresponding pin, the interrupt
request occurs respectively.
When an effective rising edge or falling edge is input, “1” is set to the corresponding bit of P14 event
register (Address: 02F616). By reading the register after the interrupt occurs, the pin, which the effec-
tive edge is input, can be confirmed even if the status of that pin has been changed.
At the completion of the reading of P14 event register, the bits, whose value is “1” in reading, will be
cleared automatically. A dummy write clears the register too.
The registers, the block diagram and the timing of key input interrupt 1 are shown in Fig. DD-15, Fig.
DD-16 and Fig. DD-17 respectively.
After changing the enable/disable setting of key input interrupt1 register or changing the effective edge
by modifying key input interrupt 1 edge selection register, the value of P14 event register and interrupt
request bit may become “1”. A dummy write to the P14 event register and a clear to the interrupt
request bit should be done after changing the effective edge.
P14 event register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
KIN1EV
Address
02F616
Bit symbol
Bit name
KIN1EV0 P14 event bit 0
KIN1EV1 P14 event bit 1
KIN1EV2 P14 event bit 2
KIN1EV3 P14 event bit 3
KIN1EV4 P14 event bit 4
KIN1EV5 P14 event bit 5
KIN1EV6 P14 event bit 6
KIN1EV7 P14 event bit 7
When reset
0016
Function
0 : Factor
1 : No factor
0 : Factor
1 : No factor
0 : Factor
1 : No factor
0 : Factor
1 : No factor
0 : Factor
1 : No factor
0 : Factor
1 : No factor
0 : Factor
1 : No factor
0 : Factor
1 : No factor
RW
Fig.DD-14 P14 event register
Rev.1.00 Jul 16, 2004 page 58 of 266
REJ03B0100-0100Z