M16C6KA_15 Datasheet, PDF (33/270 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description

M16C/6KA Group
Clock Generating Circuit
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616).
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock
oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716).
Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit de-
faults to “1” when shifting from high speed mode or mid-speed mode to stop mode and after a reset.
(2) BCLK
The BCLK is the clock that drives the CPU, and is either the main clock or is derived by dividing the main
clock by 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset.
When shifting from high speed mode or mid-speed mode to stop mode, the main clock division select bit (bit
6 at 000616) is set to “1”.
(3) Peripheral function clock
f1, f8, f32, f1SIO2, f8SIO2, f32SIO2, fAD
The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The peripheral
function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit
(bit 2 at 000616) to “1” and then executing a WAIT instruction.
Rev.1.00 Jul 16, 2004 page 31 of 266
REJ03B0100-0100Z