M16C6KA_15 Datasheet, PDF (108/270 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description

M16C/6KA Group
Clock asynchronous serial I/O (UART) mode
(a) Function for switching serial data logic
When the data logic selection bit is assigned 1, data is inverted in writing to the transmission buffer register
or reading the reception buffer register. Fig.GA-16 shows the example of timing for switching serial data
logic.
• When LSB first, parity enabled, one stop bit
Transfer clock ^{“H”}
“L”
TxD1 ^{“H”}
(no reverse) _{“L”}
TxD1 “H”
(reverse) _{“L”}
ST D0 D1 D2 D3 D4 D5 D6 D7 P ^SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST : Start bit
P : Even parity
SP : Stop bit
Fig.GA-16 Timing for switching serial data logic
(b) TxD, RxD I/O polarity switching function
This function is to reverse TXD pin output and RXD pin input. The level of any data to be input or output
(including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) for usual
use.
Rev.1.00 Jul 16, 2004 page 106 of 266
REJ03B0100-0100Z