M16C6KA_15 Datasheet, PDF (102/270 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description

M16C/6KA Group
Clock asynchronous serial I/O (UART) mode
(2) Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables.GA-5 and GA-6 list the specifications of the UART mode. Fig.GA-13 shows the UART1
transmit/receive mode register.
Table.GA-5 Specifications of UART Mode (1)
Item
Specification
Transfer data format
• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
Transfer clock
• When internal clock is selected (bit 3 at address 03A816 = “0”) :
fi/16(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at address 03A816 =“1”) :
fEXT/16(n+1)(Note 1) (Note 2)
_______ _______
Transmission/reception control • Selecting from Disable CTS, RTS function
Transmission start condition • To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at address 03AD16) = “1”
- Transmit buffer empty flag (bit 1 at address 03AD16) = “0”
_______
_______
- When CTS function is selected CTS input level = “L”
Reception start condition • To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at address 03AD16) = “1”
- Start bit detection
Interrupt request
• When transmitting
generation timing
- Transmit interrupt factor selection bit (bit 1 at address 03B016) = “0”:
At the completion of data transferring from UART1 transfer buffer register to
UART1 transmit register
- Transmit interrupt factor selection bit (bit 1 at address 03B016) = “1”:
At the completion of data transmission from UART1 transfer register
• When receiving
- At the completion of data transferring from UART1 receive register to
UART1 receive buffer register
Error detection
• Overrun error (Note 3)
This error occurs when the bit prior to the stop bit of next data is received
before the contents of UART1 receive buffer register are read out.
• Framing error
This error occurs when the number set for stop bits is not detected
• Parity error
This error occurs in the case that parity is enabled and the number of "1" in
parity bit and character bits does not match the number of "1" in parity odd/
even setting.
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UART1 bit rate register.
Note 2: fEXT is input from the CLK1 pin.
Note 3: If an overrun error occurs, the UART1 receive buffer will have the next data written in. Also note
that the UART1 receive interrupt request bit is not set to “1”.
Rev.1.00 Jul 16, 2004 page 100 of 266
REJ03B0100-0100Z