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32192 Datasheet, PDF (966/1044 Pages) Renesas Technology Corp – MCU
23
ELECTRICAL CHARACTERISTICS
23.9 A.C. Characteristics (when VCCE = 5 V)
(18) DRI Timing
a) When Special mode is off
Symbol
Parameter
Rated Value
MIN
MAX
Unit See Fig.
23.9.20
tw(DIN) DIN Input pulse width DIN0, DIN1, DIN2, DIN3, DIN4
1.5 x tc(BCLK)
ns [138]
tc(DCAP) Import period
When Input data bus width is 8, 16 bit 3.5 x tc(BCLK)
When Input data bus width is 32 bit 4 x tc(BCLK)
ns
[139]
ns
When DIN2, DIN3, DIN4 are selected
tsu(DD-E) DD Input - Import Edge in Inport event
20
Set up time (Note 1) When DIN5 is selected in Inport event
40
ns [140]
ns
When DIN2, DIN3, DIN4 are selected
th(E-DD) Import Edge - DD Input in Inport event
Hold time (Note 1)
When DIN5 is selected in Inport event
15 + tc(BCLK)
15 + tc(BCLK)
ns [141]
ns
Edge interval that
ts(E-E)
Event detection is
not simultaneous
DIN0, DIN1, DIN2, DIN3, DIN4
15 + tc(BCLK)
ns [142]
Note 1: This standard value is when considering Inport timing as a default setup. If it is not, standard value is considered with
the point that is shifted back from standard edge for tv(BCLK).
b) When Special mode is on
Symbol
Parameter
tw(DIN) DIN Input pulse width DIN0, DIN1, DIN2, DIN3, DIN4
Rated Value
MIN
MAX
1.5 x tc(BCLK)
DIN3
0.8 x tc(BCLK)
tc(DCAP) Import period
When Input data bus width is 8, 16 bit 2 x tc(BCLK)
tsu(DD-E) DD Input - Import Edge When DIN3 is selected in Inport event
20
Set up time
th(E-DD) Import Edge - DD Input When DIN3 is selected in Inport event
20
Hold time
Edge interval that
ts(E-E) Event detection is
not simultaneous
DIN0, DIN1, DIN2, DIN4
15 + tc(BCLK)
Indefinite period of DIN3
tar Sampling Edge by DIN1 before
20
exiting reset initializing level
Indefinite period of DIN3
tbr Sampling Edge by DIN1 after
20
exiting reset initializing level
Unit See Fig.
23.9.20
ns [138]
ns
ns [139]
ns [140]
ns [141]
ns [142]
ns [143]
ns [144]
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
23-40