32192 Datasheet, PDF (282/1044 Pages) Renesas Technology Corp – MCU

9
DMAC
9.2 DMAC Related Registers
[DMnCNT1 Register]
(1) SADBNx (DMAn Source Address Bank Select) bits (Bits 8, 9)
These bits select a source address bank to be used from among Bank 0, Bank 1 and Bank 2. But no bank
exsits in 32196, setting Bank2(A14=1, A15=0) is prohibited. Because Bank1 and Bank2 do not exist in the
32195, setting Bank1 and Bank2 is prohibited. And also no transfer over the bank is carried out. Upon
completion of bank transfer to the final address, the bank is then to be transferred to the head address.
(2) DADBNx (DMAn Destination Address Bank Select) bits (Bits 10, 11)
These bits select a destination address bank to be used from among Bank 0, Bank 1 and Bank 2. But no
bank exsits in 32196, setting Bank2(A14=1, A15=0) is prohibited. Because Bank1 and Bank2 do not exist in
the 32195, setting Bank1 and Bank2 is prohibited. And also no transfer over the bank is carried out. Upon
completion of bank transfer to the final address, the bank is then to be transferred to the head address.
(3) REQESELn (Extended DMAn Transfer Request Source Select) bits (Bits 12–15)
These bits select the cause or source of extended DMA transfer request on each DMA channel.
Note: • The extended DMA transfer request sources selected by the REQESELn (Extended DMAn
Transfer Request Source Select) bits have no effect unless the “Extended” DMA transfer re-
quest source is selected with the DMA Channel Control Register’s DMA Request Source Se-
lect (REQSLn) bits.
[DMnCNT2 Register]
(1) SELFEN (DMAn Self Channel Transfer Select ) bit (Bit 8)
Clearing this bit to “0” disables self channel transfer, and setting it to “1” enables self channel transfer. In
case where self channel transfer was allowed, the DMA transfer request occurs for the self channel each
time single DMA transfer is completed if the initial transfer request arises, and DMA transfer is carried out
until all transfers are completed (transfer count register underflow).
However the control of internal bus is relinquished each time single DMA transfer is completed.
And if set DMA transfer n times, DMA transfer request is occured for its channel after completing all DMA
transfer, so that it is necessary to pay attention of clearing DMA transfer request or so on when DMA
transfer is started again.
(2) RINGSEL (DMAn Rign Buffer Select) bit (Bits 10–15)
These bits select the number of DMA transfers to each channel in the ring buffer mode from among 32, 16,
8, 4 and 2 times.
In the ring buffer mode, after transfer from the transfer start address, the bit returns to the transfer start
address again, and the same operation is repeated by the number of transfers thus selected. In the ring
buffer mode, the transfer count register is placed in the free run mode, and transfer operation is continued
until the transfer enable bit is cleared to “0” (transfer disable).
Also, the DMA transfer-completed interrupt request does not arise during ring buffer mode.
Notes: • When the self channel transfer was allowed during ring buffer mode setting, care must be
exercised to its endless transfer.
• The transfer start address must be as follows:
Transfer Size: 8 bits
32-time ring buffer mode Low order 5 bits – B’00000
16-time ring buffer mode Low order 4 bits – B’0000
8-time ring buffer mode Low order 3 bits – B’000
4-time ring buffer mode Low order 2 bits – B’00
2-time ring buffer mode Low order 1 bits – B’0
Transfer Size: 16 bits
Low order 6 bits – B’000000
Low order 5 bits – B’00000
Low order 4 bits – B’0000
Low order 3 bits – B’000
Low order 2 bits – B’00
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
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