32192 Datasheet, PDF (423/1044 Pages) Renesas Technology Corp – MCU

10
MULTIJUNCTION TIMERS
10.4 TIO (Input/Output-Related 16-Bit Timer)
10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction Function)
(1) Outline of TIO delayed single-shot output mode
In delayed single-shot output mode, the timer generates a pulse in width of "reload 0 register set value + 1"
after a finite time equal to "counter set value + 1" only once and then stops.
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the
counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the
count clock. At the cycle after the first counter underflow, it is loaded with "the reload 0 register value -1" and
continues counting down. The counter stops when it underflows next time.
The F/F output waveform in delayed single-shot output mode is inverted (F/F output level changes from "L"
to "H" or vice versa) when the counter underflows first time and next, generating a single-shot pulse wave-
form in width of "reload 0 register set value + 1" after a finite time equal to "first set value of counter + 1" only
once.
Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TIO8
and TIO9) upon the first and next underflows of the counter.
The "counter set value + 1" and "reload 0 register set value + 1" are effective as count values. (For counting
operation, see also Section 10.3.10, “Operation of TOP Delayed Single-shot Output Mode.”)
(2) Notes on using TIO delayed single-shot output mode
The following describes precautions to be observed when using TIO delayed single-shot output mode.
• If the counter stops due to an underflow in the same clock period as the timer is enabled by external input,
the former has priority so that the counter stops.
• If the counter stops due to an underflow in the same clock period as count is enabled by writing to the
enable bit, the latter has priority so that count is enabled.
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the
enable bit, the latter has priority so that count is disabled.
• If the counter is accessed for read ar the cycle of underflow, the counter value is read out as H’FFFF but
changes to "reload register value -1" at the next count clock timing.
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
10-119