32192 Datasheet, PDF (817/1044 Pages) Renesas Technology Corp – MCU

16
NON-BREAK DEBUG (NBD)
16.5 RAM Monitor Function
16.5.2 NBDD Data Format
The following describes the content of each packet/field which are input to or output from the NBDD3–NBDD0 pins.
(1) Command packet (input)
Table 16.5.1 Bit Assignments of a Command Packet
Bit arrangement
Input
order ^{Field name} NBDD3 NBDD2 NBDD1 NBDD0
√^{: Necessary, -: Unnecessary}
When accessing NBD space
When accessing CPU space
During
During
During
During read During write During read _{8-bit write 16-bit write 32-bit write}
First Extension field aux3
aux2
aux1
aux0
√
√
√
√
√
√
Control field SIZ1
SIZ0
R/W
I/T
√
√
√
√
√
√
A28
A29
A30
A31
−
−
√
√
√
√
A24
A25
A26
A27
−
−
√
√
√
√
A20
A21
A22
A23
−
−
√
√
√
√
A16
A17
A18
A19
Address field
−
−
√
√
√
√
A12
A13
A14
A15
−
−
√
√
√
√
A8
A9
A10
A11
√
√
√
√
√
√
A4
A5
A6
A7
√
√
√
√
√
√
A0
A1
A2
A3
√
√
√
√
√
√
D28
D29
D30
D31
−
−
−
−
−
√
D24
D25
D26
D27
−
−
−
−
−
√
D20
D21
D22
D23
−
−
−
−
−
√
Write data D16
D17
D18
D19
−
−
−
−
−
√
field
D12
D13
D14
D15
−
−
−
−
√
√
D8
D9
D10
D11
−
−
−
−
√
√
D4
D5
D6
D7
−
√
−
√
√
√
Last
D0
D1
D2
D3
−
√
−
√
√
√
1) Extension field
Bit Name
Function
Content
aux3
Reserved for future extension
Set to "0"
aux2
Reserved for future extension
Set to "0"
aux1
Reserved for future extension
Set to "0"
aux0
Reserved for future extension
Set to "0"
Note 1: If these bits are set otherwise, device operation cannot be guaranteed.
2) Control field
Bit Name
Function
Content
SIZ1, SIZ0
Specify access size
SIZ1 SIZ0
0
0
0
1
1
0
1
1
8-bit (Note 1)
16-bit
32-bit
Settings inhibited
R/W
Specify read/write
0: Read
1: Write
I/T
Specify access space
0: Access NBD space
1: Access CPU space
Note 1: When the NBD space access is selected (I/T = "0"), only 8-bit access is accepted. If these bits are set otherwise, device
operation cannot be guaranteed.
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
16-9