32192 Datasheet, PDF (527/1044 Pages) Renesas Technology Corp – MCU

11
A/D CONVERTER
11.2 A/D Converter Related Registers
11.2.3 A/D Single Mode Register 2
A/D0 Single Mode Register 2 (AD0SIM2)
<Address: H’0080 0083>
b8
9
10 11 12 13 14 b15
AD0SH2 AD0SH2ST
AD0SEL2
0
0
0
0
0
0
0
0
<Upon exiting reset: H’00>
b
Bit Name
Function
RW
8
ADSH2
0: Simultaneous sampling invalid
A/D simultaneous sampling select bit (Note 1) 1: Simultaneous sampling valid
RW
9
ADSH2ST
0: 2nd simultaneous sampling conversion not in progress R –
A/D simultaneous sampling status bit (Note 2) 1: 2nd simultaneous sampling conversion in progress
10, 11 No function assigned. Fix to "0."
R0
12–15 ADSEL2
0000 : No channels selected
RW
A/D simultaneous sampling analog input pin
|
|
select bit (Note 3)
0011 : No channels selected
1100 : Select AD0IN12
1101 : Select ADi0N13
1110 : Select ADi0N14
1111 : Select ADi0N15
Note 1: The A/D conversion mode/sample-and-hold function must be effective with single mode register 1. When the comparator
mode/sample-and-hold function is invalid, set the AD0SH2 to "0" (Simultaneous sampling invalid).
Note 2: The second conversion speed is the same as the first conversion speed.
Note 3: When simultaneous sampling valid is selected, select from B'1100 to B'1111. Furthermore, when simultaneous sampling
invalid is seledted, select from B'0000 to B'1011.
The A/D single mode register 2 is provided to select simultaneous sampling valid or invalid in the single mode
of A/D converter and analog input pin sampled at the same time.
(1) ADSH2 (A/D Simultaneous Sampling Select) bit (Bit 8)
This bit selects whether simultaneous sampling is valid or invalid” when the A/D converter is in single mode.
By clearing this bit to “0,” simultaneous sampling becomes invalid and by setting it to “1,” simultaneous
sampling becomes valid.
(2) ADSH2ST (A/D Simultaneous Sampling Status) bit (Bit 9)
This bit indicates that the number of times the A/D conversion is executed when simultaneous sampling is
effective. The bit is set to "1" only when second conversion is in progress.
(3) ADSEL2 (A/D Simultaneous Sampling Analog Input Pin Select) bit (Bits 12–15)
These bits select a channel sampled at the same time when simultaneous sampling is effective.
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
11-21