32192 Datasheet, PDF (330/1044 Pages) Renesas Technology Corp – MCU

10
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
TIN24,25 Input Processing Control Register (TIN2425CR)
b8
9
10
11
12
13
14
b15
TIN25S
TIN24S
0
0
0
0
0
0
0
0
b
8–11
12, 13
14, 15
Bit Name
No function assigned. Fix to "0."
TIN25S (TIN25 input processing select bit)
TIN24S (TIN24 input processing select bit)
Function
00: Disable input
01: Rising edge
10: Falling edge
11: Both edges
<Address: H’0080 07E1>
<Upon exiting reset: H’00>
RW
00
RW
TIN26,27 Input Processing Control Register (TIN2627CR)
b8
9
10
11
12
13
14
b15
TIN27S
TIN26S
0
0
0
0
0
0
0
0
b
8–11
12, 13
14, 15
Bit Name
No function assigned. Fix to "0."
TIN27S (TIN27 input processing select bit)
TIN26S (TIN26 input processing select bit)
Function
00: Disable input
01: Rising edge
10: Falling edge
11: Both edges
<Address: H’0080 0BE1>
<Upon exiting reset: H’00>
RW
00
RW
10.2.6 Output Flip-flop Control Unit
The Output Flip-flop Control Unit controls the flip-flops (F/F) provided for each timer. Following flip-flop control
registers are included:
• F/F Source Select Register 0 (FFS0)
• F/F Source Select Register 1 (FFS1)
• F/F Protect Register 0 (FFP0)
• F/F Protect Register 1 (FFP1)
• F/F21–28 Protect Register (FF2128P)
• F/F29–36 Protect Register (FF2936P)
• F/F Data Register 0 (FFD0)
• F/F Data Register 1 (FFD1)
• F/F21–28 Data Register (FF2128D)
• F/F29–36 Data Register (FF2936D)
The timing at which signals are generated to the output flip-flop by each timer are shown in Table 10.2.5. (Note
that this timing is different from one at which signals are output from the timer to the output event bus.)
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
10-26