32192 Datasheet, PDF (823/1044 Pages) Renesas Technology Corp – MCU

17
EXTERNAL BUS INTERFACE
17.1 Outline of the External Bus Interface
(6) Data Bus (DB0–DB15)
This is the 16-bit bus used to access external devices. During external read access, data is latched from the
bus synchronously with the rising edge of the read strobe. Even during 8-bit read, 16-bit data is always read
in, but data only on the valid byte position is transferred into the internal circuit. During external write access,
data is output from the bus. During 8-bit write, the valid byte position to write is indicated by the output signal
BHW# or BLW#. When accessing the internal area, the bus functions as an input bus.
Note: • During external extension mode, these pins are switched for port upon exiting reset. Their pin
functions must be set for data bus using the corresponding Port Operation Mode Register as
necessary.
(7) System Clock/Write (CLKOUT/WR#)
The pin function changes depending on the Bus Mode Control Register (BUSMODC).
When BUSMOD = "0" and this signal is System Clock (CLKOUT), the system clock necessary to synchro-
nize operations in external systems is output from the pin. If the CPU clock is 160 MHz, and the CLKOSEL
(CLKOUT select) bit in the CLKOUT select register is set to “0,” a 20 MHz clock is output; if the CLKOSEL
bit is set to “1,” a 40 MHz clock is output. Furthermore, if the CLKOUT/WR# function is unused, and P70MD
in the P7 Operation Mode Register is cleared to “0,” the pin can be used as P70; if P150MD in the P15
Operation Mode Register is cleared to “0,” the pin can be used as P150.
When BUSMOD = "1" and this signal is Write (WR#), during external write access it indicates the valid data
transferred on the data bus. During external read cycle and when accessing the internal area it outputs a "H."
Note: • During external extension mode, this pin is switched for port upon exiting reset. Its pin function must
be set for system clock/write using the corresponding Port Operation Mode Register as necessary.
(8) Wait (WAIT#)
When the 32192 started an external bus cycle, it automatically inserts wait states while the WAIT# input
signal is asserted. For details, see Chapter 18, “Wait Controller.” If the WAIT function is unused, and
P71MD in the P7 Operation Mode Register is cleared to “0,” the pin can be used as P71; if P153MD in the
P15 Operation Mode Register is cleared to “0,” the pin can be used as P153.
Note: • During external extension mode, this pin is switched for port upon exiting reset. Its pin function
must be set for wait using the corresponding Port Operation Mode Register as necessary.
(9) Hold Control (HREQ#, HACK#)
The hold state means internal bus and external bus stop accessing the bus and the bus interface related
pins are tristated (high impedance). While the microcomputer is in a hold state, any bus master external to
the chip can use the system bus to transfer data. Even during hold status the command in which command
que is done though, if the command with access to bus is done, the command performance operation is
stopped at that time.
An "L" signal input on the HREQ# pin places the microcomputer into a hold state. While the microcomputer
remains in a hold state after accepting the hold request and during a transition to the hold state, the HACK#
pin outputs a "L" level signal. To exit the hold state and return to normal operating state, release the HREQ#
signal back "H."
Note: • During external extension mode, these pins are switched for port upon exiting reset. Their pin functions
must be set for hold control using the corresponding Port Operation Mode Register as necessary.
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
17-3