32192 Datasheet, PDF (340/1044 Pages) Renesas Technology Corp – MCU

10
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
Example for clearing interrupt request status
Initial state
Interrupt request status
b4 5 6 b7
0000
Event occurs on bit 6
0010
Interrupt request
Event occurs on bit 4
Write to the interrupt request status
b4 5 6 b7
1101
1010
1000
Only bit 6 cleared
Bit 4 data retained
Program example
• To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1, ISTAT1 (0x02 bit)
ISTREG = 0xfd;
/* Clear ISTAT1 (0x02 bit) only */
To clear an interrupt request status, always be sure to write "1" to all other interrupt request status bits. At this time,
avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation
and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared.
ISTREG &= 0xfd;
/* Clear ISTAT1 (0x02 bit) only */
Event occurs on bit 6
Interrupt request status
b4 5 6 b7
0010
Read
0010
Event occurs on bit 4
1010
Clear bit 6 (ANDing with 1101)
0000
0000
Write
Only bit 6 cleared
Bit 4 also cleared
Figure 10.2.5 Example for Clearing Interrupt Request Status
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
10-36