32192 Datasheet, PDF (775/1044 Pages) Renesas Technology Corp – MCU

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Data
synchronous signal
Data
Figure 14.2.3 Data Transfer Method 1
DIRECT RAM INTERFACE (DRI)
14.2 DRI Related Registers
Data
synchronous signal
Data
Figure 14.2.4 Data Transfer Method 2
DIN1 (Note 1)
Data synchronous signal
(DIN3)
Data
Output signal to the event
detection unit (Note 2)
Output signal to
the data capture unit
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6
DATA0, DATA1 DATA2, DATA3 DATA4, ...
Note 1: When "L" level is selected in SPISL bit of DRI special mode register (DRISPMOD)
Note 2: Select falling detection to DIN3ED (DIN3 event detection control) bit of DIN input
processing control register (DINCNT).
Figure 14.2.5 Timing Chart when Special Mode is On (DIN3 Sampling Edge: Rise)
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
14-17