R01DS0190EJ0100 Datasheet, PDF (94/110 Pages) Renesas Technology Corp – 32 MHz 32-bit RX MCUs, 50 DMIPS, up to 128 Kbytes of flash memory

RX111 Group
5. Electrical Characteristics
5.8 Power-On Reset Circuit and Voltage Detection Circuit Characteristics
Table 5.43 Power-On Reset Circuit and Voltage Detection Circuit Characteristics (1)
Conditions: VCC = AVCC0 = VCC_USB, VSS = AVSS0 = VREFL0 = VSS_USB = 0 V, T_a = –40 to +105°C
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Voltage detection level Power-on reset (POR)
V_POR
1.35
1.50
1.65
V
Figure 5.51,
Figure 5.52
Voltage detection
circuit (LVD1)*¹
V_{det1_4}
V_{det1_5}
V_{det1_6}
V_{det1_7}
V_{det1_8}
V_{det1_9}
V_{det1_A}
V_{det1_B}
V_{det1_C}
V_{det1_D}
3.00
2.91
2.81
2.70
2.60
2.50
2.40
1.99
1.90
1.80
3.10
3.00
2.90
2.79
2.68
2.58
2.48
2.06
1.96
1.86
3.20
3.09
2.99
2.88
2.76
2.66
2.56
2.13
2.02
1.92
V
Figure 5.53
At falling edge VCC
Note: • These characteristics apply when noise is not superimposed on the power supply. When a setting is made so that the voltage
detection level overlaps with that of the voltage detection circuit (LVD2), it cannot be specified which of LVD1 and LVD2 is used
for voltage detection.
Note 1. # in the symbol Vdet1_# denotes the value of the LVDLVLR.LVD1LVL[3:0] bits.
Table 5.44 Power-On Reset Circuit and Voltage Detection Circuit Characteristics (2)
Conditions: VCC = AVCC0 = VCC_USB, VSS = AVSS0 = VREFL0 = VSS_USB = 0 V, T_a = –40 to +105°C
Item
Symbol Min. Typ. Max. Unit
Test Conditions
Voltage detection level
Voltage detection circuit
(LVD2)*¹
Wait time after power-on At normal startup*³
reset cancellation
During fast startup time*⁴
Wait time after voltage
monitoring 1 reset
cancellation
Power-on voltage monitoring
1 reset disabled*³
Power-on voltage monitoring
1 reset enabled*⁴
Wait time after voltage monitoring 2 reset cancellation
Response delay time
Minimum VCC down time*⁵
V_{det2_0}
V_{det2_1}
V_{det2_2}
V_{det2_3}*²
t_POR
t_POR
t_LVD1
t_LVD2
t_det
t_VOFF
2.71
2.43
1.87
1.69
―
―
―
―
―
―
350
Power-on reset enable time
LVD operation stabilization time (after LVD is enabled)
Hysteresis width (LVD1 and LVD2)
t_W(POR)
1
Td_(E-A)
―
V_LVH
―
―
―
―
2.90
2.60
2.00
1.80
9.1
1.6
568
100
100
―
―
―
―
70
60
50
40
3.09
2.77
2.13
1.91
―
―
―
―
―
350
―
―
300
―
―
―
―
V
Figure 5.54
At falling edge VCC
ms Figure 5.52
μs Figure 5.53
μs Figure 5.54
μs Figure 5.51
μs Figure 5.51,
VCC = 1.0 V or above
ms Figure 5.52,
VCC = below 1.0 V
μs Figure 5.53, Figure 5.54
mV Vdet1_4 selected
Vdet1_5 to 9, LVD2 selected
When selection is from
among Vdet1_A to B.
When selection is from
among Vdet1_C to D.
Note: • These characteristics apply when noise is not superimposed on the power supply. When a setting is made so that the voltage
detection level overlaps with that of the voltage detection circuit (LVD1), it cannot be specified which of LVD1 and LVD2 is used
for voltage detection.
Note 1. # in the symbol Vdet2_# denotes the value of the LVDLVLR.LVD2LVL[3:0] bits.
Note 2. Vdet2_3 selection can be used only when the CMPA2 pin input voltage is selected and cannot be used when the power supply
voltage (VCC) is selected.
Note 3. When OFS1.(STUPLVD1REN, FASTSTUP) = 11b.
Note 4. When OFS1.(STUPLVD1REN, FASTSTUP) ≠ 11b.
Note 5. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels V_POR, V_det0,
V_det1, and V_det2 for the POR/LVD.
R01DS0190EJ0100 Rev.1.00
Jun 19, 2013
Page 94 of 107