R01DS0190EJ0100 Datasheet, PDF (78/110 Pages) Renesas Technology Corp – 32 MHz 32-bit RX MCUs, 50 DMIPS, up to 128 Kbytes of flash memory

RX111 Group
5. Electrical Characteristics
Table 5.32 Timing of On-Chip Peripheral Modules (3)
Conditions: VCC = AVCC0 = VCC_USB = 1.8 to 3.6 V, VSS = AVSS0 = VREFL0 = VSS_USB = 0 V, T_a = –40 to +105°C
Item
Symbol
Min.
Max.
Unit*¹ Test Conditions
Simple SCK clock cycle output (master)
SPI
SCK clock cycle input (slave)
t_SPcyc
4
65536
t_Pcyc Figure 5.41
6
65536
SCK input clock high pulse width
SCK input clock low pulse width
SCK clock rise/fall time
Data input setup time (master) 2.7 V or above
1.8 V or above
t_SPCKWH
0.4
t_SPCKWL
0.4
t_SPCKr, t_SPCKf
—
t_SU
65
95
0.6
t_SPcyc
0.6
t_SPcyc
20
ns
—
ns Figure 5.42,
—
Figure 5.43
Data input setup time (slave)
40
—
Data input hold time
SSL input setup time
SSL input hold time
Data output delay time (master)
Data output delay time (slave) 2.7 V or above
t_H
t_LEAD
t_LAG
t_OD
40
—
ns
3
—
t_Pcyc
3
—
t_Pcyc
—
40
ns
—
65
1.8 V or above
—
85
Data output hold time (master)
2.7 V or above
1.8 V or above
t_OH
–10
—
ns
–20
—
Data output hold time (slave)
–10
—
Data rise/fall time
SSL input rise/fall time
Slave access time
Slave output release time
t_Dr, t_Df
—
t_SSLr, t_SSLf
—
t_SA
—
t_REL
—
20
ns
20
ns
6
t_Pcyc Figure 5.44,
6
t_Pcyc ^{Figure 5.45}
Note 1. t_Pcyc: PCLK cycle
R01DS0190EJ0100 Rev.1.00
Jun 19, 2013
Page 78 of 107