English
Language : 

R01DS0190EJ0100 Datasheet, PDF (77/110 Pages) Renesas Technology Corp – 32 MHz 32-bit RX MCUs, 50 DMIPS, up to 128 Kbytes of flash memory
◁
RX111 Group
5. Electrical Characteristics
Table 5.31 Timing of On-Chip Peripheral Modules (2)
Conditions: VCC = AVCC0 = VCC_USB = 1.8 to 3.6 V, VSS = AVSS0 = VREFL0 = VSS_USB = 0 V, Ta = –40 to +105°C,
C = 30 pF
RSPI RSPCK clock
cycle
RSPCK clock
high pulse width
Item
Master
Slave
Master
Slave
RSPCK clock
low pulse width
Master
Slave
RSPCK clock
rise/fall time
Output 2.7 V or above
1.8 V or above
Input
Data input setup
time
Master 2.7 V or above
1.8 V or above
Slave
Data input hold
time
Master RSPCK set to a
division ratio other than
PCLKB divided by 2
RSPCK set to PCLKB
divided by 2
Slave
SSL setup time
Master
Slave
SSL hold time
Master
Slave
Data output delay Master 2.7 V or above
time
1.8 V or above
Slave 2.7 V or above
1.8 V or above
Data output hold
time
Master 2.7 V or above
1.8 V or above
Slave
Successive
Master
transmission delay Slave
time
MOSI and MISO
rise/fall time
Output 2.7 V or above
1.8 V or above
Input
SSL rise/fall time Output
Input
Slave access time
2.7 V or above
1.8 V or above
Slave output release time 2.7 V or above
1.8 V or above
Symbol
Min.
tSPcyc
tSPCKWH
tSPCKWL
tSPCKr,
tSPCKf
tSU
tH
2
8
(tSPcyc – tSPCKr –
tSPCKf)/2 – 3
(tSPcyc – tSPCKr –
tSPCKf)/2
(tSPcyc – tSPCKr–
tSPCKf)/2 – 3
(tSPcyc – tSPCKr –
tSPCKf)/2
—
—
—
10
30
25 – tPcyc
tPcyc
Max.
4096
4096
—
—
—
—
10
15
1
—
—
—
—
tHF
0
—
tH
tLEAD
tLAG
tOD
tOH
tTD
20 + 2 × tPcyc
—
–30 + N*2 × tSPcyc
—
2
—
–30 + N*3 × tSPcyc
—
2
—
—
14
—
30
—
3 × tPcyc + 65
—
3 × tPcyc +105
0
—
–20
—
0
—
tSPcyc + 2 × tPcyc
4 × tPcyc
8 × tSPcyc + 2 × tPcyc
—
tDr, tDf
—
10
—
20
—
1
tSSLr,
—
20
tSSLf
—
1
tSA
—
6
—
7
tREL
—
5
—
6
Unit
tPcyc
*1
ns
ns
ns
μs
ns
ns
ns
tPcyc
ns
tPcyc
ns
ns
ns
ns
μs
ns
μs
tPcyc
tPcyc
Test
Conditions
Figure 5.41
Figure 5.42 to
Figure 5.45
Figure 5.44,
Figure 5.45
Note 1. tPcyc: PCLK cycle
Note 2. N: An integer from 1 to 8 that can be set by the RSPI clock delay register (SPCKD)
Note 3. N: An integer from 1 to 8 that can be set by the RSPI slave select negation delay register (SSLND)
R01DS0190EJ0100 Rev.1.00
Jun 19, 2013
Page 77 of 107
 ▷