R01DS0190EJ0100 Datasheet, PDF (76/110 Pages) Renesas Technology Corp – 32 MHz 32-bit RX MCUs, 50 DMIPS, up to 128 Kbytes of flash memory

RX111 Group
5. Electrical Characteristics
5.3.5
Timing of On-Chip Peripheral Modules
Table 5.30 Timing of On-Chip Peripheral Modules (1)
Conditions: VCC = AVCC0 = VCC_USB = 1.8 to 3.6 V, VSS = AVSS0 = VREFL0 = VSS_USB = 0 V, T_a = –40 to +105°C
Item
Symbol
Min.
Max. Unit*¹
Test
Conditions
I/O ports Input data pulse width
MTU2 Input capture input pulse width
t_PRW
1.5
Single-edge setting
t_TICW
1.5
Both-edge setting
2.5
—
t_Pcyc Figure 5.33
—
t_Pcyc Figure 5.34
—
Timer clock pulse width
Single-edge setting
t_TCKWH,
1.5
Both-edge setting
t_TCKWL
2.5
—
t_Pcyc Figure 5.35
—
Phase counting mode
2.5
—
POE
SCI
POE# input pulse width
Input clock cycle
t_POEW
1.5
Asynchronous
t_Scyc
4
Clock synchronous
6
—
t_Pcyc Figure 5.36
—
t_Pcyc Figure 5.37
—
Input clock pulse width
Input clock rise time
Input clock fall time
Output clock cycle
t_SCKW
0.4
t_SCKr
—
t_SCKf
—
Asynchronous
t_Scyc
16
Clock synchronous
4
0.6
t_Scyc
20
ns
20
ns
—
t_Pcyc Figure 5.38
—
Output clock pulse width
Output clock rise time
Output clock fall time
Transmit data delay time
(master)
Transmit data delay time
(slave)
Clock synchronous
Clock
2.7 V or above
synchronous _{1.8 V or above}
t_SCKW
0.4
t_SCKr
—
t_SCKf
—
t_TXD
—
0.6
t_Scyc
20
ns
20
ns
40
ns
—
65
ns
—
100
ns
Receive data setup time Clock
2.7 V or above
(master)
synchronous _{1.8 V or above}
t_RXS
65
—
ns
90
—
ns
Receive data setup time Clock synchronous
(slave)
40
—
Receive data hold time Clock synchronous
t_RXH
40
—
A/D
converter
CAC
Trigger input pulse width
CACREF input pulse width
t_Pcyc ≤ t_cac*²
t_TRGW
1.5
—
t_CACREF 4.5 t_cac + 3 t_Pcyc
—
t_Pcyc > t_cac*²
5 t_cac + 6.5 t_Pcyc
CLKOUT CLKOUT pin output cycle*⁴
VCC = 2.7 V or above
t_Ccyc
125
—
VCC = 1.8 V or above
250
CLKOUT pin high pulse width*³
VCC = 2.7 V or above
t_CH
35
—
VCC = 1.8 V or above
70
CLKOUT pin low pulse width*³
VCC = 2.7 V or above
t_CL
VCC = 1.8 V or above
35
—
70
CLKOUT pin output rise time
VCC = 2.7 V or above
t_Cr
VCC = 1.8 V or above
—
15
30
CLKOUT pin output fall time
VCC = 2.7 V or above
t_Cf
VCC = 1.8 V or above
—
15
30
ns
ns
t_Pcyc Figure 5.39
ns
ns
ns
ns
ns
ns
Note 1. t_Pcyc: PCLK cycle
Note 2. t_cac: CAC count clock source cycle
Note 3. When the LOCO is selected as the clock output source (CKOCR.CKOSEL[2:0] bits = 000b), set the clock output division ratio
selection to divided by 2 (CKOCR.CKODIV[2:0] bits = 001b).
Note 4. When the EXTAL external clock input or an oscillator is used with divided by 1 (CKOCR.CKOSEL[2:0] bits = 010b and
CKOCR.CKODIV[2:0] bits = 000b) to output from CLKOUT, the above should be satisfied with an input duty cycle of 45 to 55%.
R01DS0190EJ0100 Rev.1.00
Jun 19, 2013
Page 76 of 107