R01DS0190EJ0100 Datasheet, PDF (53/110 Pages) Renesas Technology Corp – 32 MHz 32-bit RX MCUs, 50 DMIPS, up to 128 Kbytes of flash memory

RX111 Group
5. Electrical Characteristics
Item
Symbol
Typ
*⁴
Max
Unit
Test
Conditions
Supply
current*¹
Low-speed
operating mode
Normal
operating
mode
No peripheral operation*⁸ ICLK = 32.768 kHz I_CC
All peripheral operation:
Normal*^9, *¹⁰
ICLK = 32.768 kHz
4.0 — μA
11.5 —
All peripheral operation:
Max.*^9, *¹⁰
ICLK = 32.768 kHz
— 40
Sleep mode No peripheral operation*⁸ ICLK = 32.768 kHz
2.2 —
All peripheral operation:
Normal*⁹
ICLK = 32.768 kHz
7.1 —
Deep sleep
mode
No peripheral operation*⁸ ICLK = 32.768 kHz
All peripheral operation:
Normal*⁹
ICLK = 32.768 kHz
1.8 —
5.3
Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up MOSs
are in the off state.
Note 2. Clock supply to the peripheral functions is stopped. This does not include BGO operation. The clock source is PLL. FCLK and
PCLK are set to divided by 64.
Note 3. Clocks are supplied to the peripheral functions. This does not include BGO operation. The clock source is PLL. FCLK and PCLK
are set to the same frequency as ICLK.
Note 4. Values when VCC = 3.3 V.
Note 5. This is the increase for programming or erasure of the ROM or flash memory for data storage during program execution.
Note 6. Clock supply to the peripheral functions is stopped. The clock source is PLL when ICLK = 12 MHz, and HOCO otherwise. FCLK
and PCLK are set to divided by 64.
Note 7. Clocks are supplied to the peripheral functions. The clock source is PLL when ICLK = 12 MHz, and HOCO otherwise. FCLK and
PCLK are set to the same frequency as ICLK.
Note 8. Clock supply to the peripheral functions is stopped. The clock source is the sub-clock oscillator. FCLK and PCLK are set to
divided by 64.
Note 9. Clocks are supplied to the peripheral functions. The clock source is the sub-clock oscillator. FCLK and PCLK are set to the same
frequency as ICLK.
Note 10. Values when the MSTPCRA.MSTPA17 bit (12-bit A/D converter module stop bit) is set to “transition to the module stop state is
made”.
20
18
Ta = 85/105°C, ICLK = 32 MHz^*2
16
14
12
Ta = 25°C, ICLK = 32 MHz^*1
10
Ta = 85/105°C, ICLK = 16 MHz^*2
8
Ta = 85/105°C, ICLK = 8 MHz^*2
6
Ta = 25°C, ICLK = 16 MHz^*1
4
Ta = 25°C, ICLK = 8 MHz^*1
2
0
1.5
2
2.5
3
3.5
4
VCC (V)
Figure 5.1
Note 1. All peripheral operation is normal. This does not include BGO operation.
Average value of the tested middle samples during product evaluation.
Note 2. All peripheral operation is maximum. This does not include BGO operation.
Average value of the tested upper-limit samples during product evaluation.
Voltage Dependency in High-Speed Operating Mode (Reference Data)
R01DS0190EJ0100 Rev.1.00
Jun 19, 2013
Page 53 of 107