R01DS0190EJ0100 Datasheet, PDF (67/110 Pages) Renesas Technology Corp – 32 MHz 32-bit RX MCUs, 50 DMIPS, up to 128 Kbytes of flash memory

RX111 Group
5. Electrical Characteristics
Table 5.22 Clock Timing
Conditions: VCC = AVCC0 = VCC_USB = 1.8 to 3.6 V, VSS = AVSS0 = VREFL0 = VSS_USB = 0 V, T_a = –40 to +105°C
Item
Symbol Min. Typ. Max. Unit Test Conditions
XTAL external clock input cycle time
t_Xcyc
50
—
—
ns Figure 5.18
XTAL external clock input high pulse width
t_XH
20
—
—
ns
XTAL external clock input low pulse width
t_XL
20
—
—
ns
XTAL external clock rising time
t_Xr
—
—
5
ns
XTAL external clock falling time
t_Xf
—
—
5
ns
XTAL external clock input wait time*¹
t_EXWT
0.5
—
—
µs
Main clock oscillator oscillation frequency*²
2.4 ≤ VCC ≤ 3.6
f_MAIN
1
—
20 MHz
1.8 ≤ VCC < 2.4
1
—
8
Main clock oscillation stabilization time (crystal)*²
t_MAINOSC
—
3
—
ms Figure 5.20
Main clock oscillation stabilization time (ceramic resonator)*²
t_MAINOSC
—
50
µs
LOCO clock oscillation frequency
f_LOCO
3.44
4.0
4.56 MHz
LOCO clock oscillation stabilization time
t_LOCO
—
—
0.5
µs Figure 5.21
IWDT-dedicated clock oscillation frequency
IWDT-dedicated clock oscillation stabilization time
f_ILOCO 12.75
15
17.25 kHz
t_ILOCO
—
—
50
μs Figure 5.19
HOCO clock oscillation frequency
f_HOCO 31.52
32
32.48 MHz Ta = –40 to 85°C
31.68 32 32.32
Ta = –20 to 85°C
31.36 32 32.64
Ta = –40 to 105°C
HOCO clock oscillation stabilization time
PLL input frequency*³
t_HOCO2
—
—
56
µs Figure 5.23
f_PLLIN
4
—
8
MHz
PLL circuit oscillation frequency*³
f_PLL
32
—
48 MHz
PLL clock oscillation stabilization time
t_PLL
—
—
50
µs Figure 5.24
Sub-clock oscillator oscillation frequency
Sub-clock oscillation stabilization time*⁴
f_SUB
t_SUBOSC
— 32.768 —
—
0.5
—
kHz
s Figure 5.25
Note 1. Time until the clock can be used after the main clock oscillator stop bit (MOSCCR.MOSTP) is set to 0 (operating) when the
external clock is stable.
Note 2. Reference values when an 8-MHz oscillator is used.
When specifying the main clock oscillator stabilization time, set the MOSCWTCR register with a stabilization time value that is
equal to or greater than the oscillator-manufacturer-recommended value.
After changing the setting of the MOSCCR.MOSTP bit so that the main clock oscillator operates, read the OSCOVFSR.MOOVF
flag to confirm that is has become 1, and then start using the main clock.
Note 3. The VCC range that the PLL can be used is 2.4 to 3.6 V.
Note 4. After changing the setting of the SOSCCR.SOSTP bit or RCR3.RTCEN bit so that the sub-clock oscillator operates, only start
using the sub-clock after the sub-clock oscillation stabilization time with an adequate margin (2 times is recommended) has
elapsed.
t_EXH
t_EXcyc
t_EXL
XTAL external clock input
t_EXr
t_EXf
Figure 5.18 XTAL External Clock Input Timing
R01DS0190EJ0100 Rev.1.00
Jun 19, 2013
VCC × 0.5
Page 67 of 107