R01DS0190EJ0100 Datasheet, PDF (9/110 Pages) Renesas Technology Corp – 32 MHz 32-bit RX MCUs, 50 DMIPS, up to 128 Kbytes of flash memory

RX111 Group
1.3 Block Diagram
Figure 1.2 shows a block diagram.
1. Overview
ROM
RAM
RX CPU
Clock
generation
circuit
ICUb
DTCa
E2 DataFlash
IWDTa
ELC
CRC
SCIe × 2 channels
SCIf × 1 channel
RSPI × 1 channel
RIIC × 1 channel
MTU2a × 6 channels
POE2a
USBc × 1 port
CMT × 2 channels (unit 0)
RTCA
12-bit A/D converter × 14 channels
Temperature sensor
8-bit D/A converter × 2 channels
DOC
CAC
BSC
External bus
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port A
Port B
Port C
Port E
Port H
Port J
ICUb:
DTCa:
IWDTa:
ELC:
CRC:
SCIe/SCIf:
RSPI:
RIIC:
Interrupt controller
Data transfer controller
Independent watchdog timer
Event link controller
CRC (cyclic redundancy check) calculator
Serial communications interface
Serial peripheral interface
I²C bus interface
MTU2a: Multi-function timer pulse unit 2
POE2a: Port output enable 2
USBc: USB 2.0 host/function module
CMT: Compare match timer
RTCA: Realtime clock
DOC: Data operation circuit
CAC: Clock frequency accuracy measurement circuit
Figure 1.2
Block Diagram
R01DS0190EJ0100 Rev.1.00
Jun 19, 2013
Page 9 of 107