R01DS0190EJ0100 Datasheet, PDF (3/110 Pages) Renesas Technology Corp – 32 MHz 32-bit RX MCUs, 50 DMIPS, up to 128 Kbytes of flash memory

RX111 Group
1. Overview
Table 1.1
Outline of Specifications (2/3)
Classification
DMA
Module/Function
Data transfer controller
(DTCa)
I/O ports
General I/O ports
Event link controller (ELC)
Multi-function pin controller (MPC)
Timers
Multi-function timer pulse
unit 2 (MTU2a)
Port output enable 2
(POE2a)
Compare match timer
(CMT)
Independent watchdog
timer (IWDTa)
Realtime clock (RTCA)
Communication
functions
Serial communications
interfaces (SCIe, SCIf)
I²C bus interface (RIIC)
Serial peripheral interface
(RSPI)
Description
 Transfer modes: Normal transfer, repeat transfer, and block transfer
 Activation sources: Interrupts
 Chain transfer function
64-pin /48-pin /40-pin /36-pin
 I/O: 46/30/24/20
 Input: 2/2/1/1
 Pull-up resistors: 38/24/19/16
 Open-drain outputs: 34/24/19/16
 5-V tolerance: 4/4/4/4
 Event signals of 35 types can be directly connected to the module
 Operations of timer modules are selectable at event input
 Capable of event link operation for port B
Capable of selecting the input/output function from multiple pins
 (16 bits × 6 channels) × 1 unit
 Time bases for the six 16-bit timer channels can be provided via up to 16 pulse-input/output lines and
three pulse-input lines
 Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than
channel 5, for which only four signals are available.
 Input capture function
 21 output compare/input capture registers
 Pulse output mode
 Complementary PWM output mode
 Reset synchronous PWM mode
 Phase-counting mode
 Capable of generating conversion start triggers for the A/D converter
Controls the high-impedance state of the MTU’s waveform output pins
 (16 bits × 2 channels) × 1 unit
 Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
 14 bits × 1 channel
 Count clock: Dedicated low-speed on-chip oscillator for the IWDT
Frequency divided by 1, 16, 32, 64, 128, or 256
 Clock source: Sub-clock
 Calendar count mode or binary count mode selectable
 Interrupts: Alarm interrupt, periodic interrupt, and carry interrupt
 3 channels (channel 1, 5: SCIe, channel 12: SCIf)
 Serial communications modes: Asynchronous, clock synchronous, and smart card interface
 On-chip baud rate generator allows selection of the desired bit rate
 Choice of LSB-first or MSB-first transfer
 Average transfer rate clock can be input from MTU2 timers
 Simple I²C
 Simple SPI
 Master/slave mode supported (SCIf only)
 Start frame and information frame are included (SCIf only)
 Start-bit detection in asynchronous mode: Low level or falling edge is selectable
 1 channel
 Communications formats:
I²C bus format/SMBus format
 Master mode or slave mode selectable
 Supports fast mode
 1 channel
 Transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPI
clock (RSPCK) signals enables serial transfer through SPI operation (four lines) or clock-
synchronous operation (three lines)
 Capable of handling serial transfer as a master or slave
 Data formats
 Choice of LSB-first or MSB-first transfer
The number of bits in each transfer can be changed to 8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24, or
32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with each frame
having up to 32 bits)
 Double buffers for both transmission and reception
R01DS0190EJ0100 Rev.1.00
Jun 19, 2013
Page 3 of 107