HD404629R Datasheet, PDF (91/157 Pages) Renesas Technology Corp – AS Microcomputer Incorporating a DTMF Generator Circuit

,Transfer completion
(IFS ← 1)
Interrupts inhibited
IFS ^← 0
SMRA write
HD404629R Series
Yes
IFS = 1?
Transmit clock
error processing
No
Normal
termination
Transmit clock error detection flowchart
Transmit clock
Transmit clock wait state
State
wait state
Transfer state
Transfer state
SCK pin (input)
SMRA write
Noise
1
2
3
4
5
6
7
8
Transfer state has been
entered by the transmit clock
error. When SMRA is written,
IFS is set.
IFS
Flag set because octal
counter reaches 000
Flag reset at
transfer completion
Transmit clock error detection procedure
Figure 73 Transmit Clock Error Detection
89