HD404629R Datasheet, PDF (130/157 Pages) Renesas Technology Corp – AS Microcomputer Incorporating a DTMF Generator Circuit

HD404629R Series
Table 35 Register-Register Instructions
Operation
Mnemonic Operation Code
Function
Words/
Status Cycles
Load A
LAB
000100 1000
B→A
1/1
from B
Load B
LBA
001100 1000
A→B
1/1
from A
Load A
LAW*
010000 0000
W→A
2/2*
from W
000000 0000
Load A
LAY
001010 1111
Y→A
1/1
from Y
Load A
LASPX
000110 1000
SPX → A
1/1
from SPX
Load A
LASPY
000101 1000
SPY → A
1/1
from SPY
Load A
LAMR m
1 0 0 1 1 1 m₃ m₂ m₁ m₀
MR (m) → A
1/1
from MR
Exchange
XMRA m
1 0 1 1 1 1 m₃ m₂ m₁ m₀
MR (m) ↔ A
1/1
MR and A
Note: * Although the LAW and LWA instructions require an operand ($000) in the second word, the
assembler generates it automatically and thus there is no need to specify it explicitly.
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