HD404629R Datasheet, PDF (88/157 Pages) Renesas Technology Corp – AS Microcomputer Incorporating a DTMF Generator Circuit

HD404629R Series
In transfer state, writing data to serial mode register A (SMRA: $005) (06, 16) initializes the serial
interface, and STS wait state is entered.
If the state changes from transfer to another state, the serial interrupt request flag (IFS: $023, bit 2) is set
by the octal counter that is reset to 000.
• Continuous clock output state (only in internal clock mode): Continuous clock output state is entered
only in internal clock mode. In this state, the serial interface does not transmit/
receive data but only outputs the transmit clock from the SCK pin.
When bits 1 and 0 (PMRA1, PMRA0) of port mode register A (PMRA: $004) are 00 in transmit clock
wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state.
If serial mode register A (SMRA: $005) is written to in continuous clock output mode (18), STS wait
state is entered.
External clock mode
STS wait state
(Octal counter = 000,
transmit clock disabled)
00 MCU reset
SMRA write 04
01 STS instruction
06 SMRA write (IFS ← 1)
Transmit clock wait state
(Octal counter = 000)
02 Transmit clock
03
8 transmit clocks
05
STS instruction (IFS ^← 1)
Transfer state
(Octal counter = 000)
Internal clock mode
SMRA write
18
STS wait state
(Octal counter = 000,
transmit clock disabled)
10 MCU reset
Continuous clock output state
(PMRA 0, 1 = 00)
SMRA write 14
11 STS instruction
Transmit clock 17
Transmit clock wait state
(Octal counter = 000)
12 Transmit clock
15
STS instruction (IFS ← 1)
13 8 transmit clocks
16 SMRA write (IFS ←1)
Transfer state
(Octal counter = 000)
Note: Refer to the Operating States section for the corresponding encircled numbers.
Figure 71 Serial Interface State Transitions
Output Level Control in Idle States: In idle states, that is, STS wait state and transmit clock wait state,
the output level of the SO pin can be controlled by setting bit 1 (SMRB1) of serial mode register B (SMRB:
$028) to 0 or 1. The output level control example is shown in figure 72. Note that the output level cannot
be controlled in transfer state.
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