HD404629R Datasheet, PDF (109/157 Pages) Renesas Technology Corp – AS Microcomputer Incorporating a DTMF Generator Circuit

HD404629R Series
LCD Duty-Cycle/Clock Control Register (LMR: $01C): Four-bit write-only register which selects the
display duty cycle and LCD clock source, as shown in figure 97. The dependence of frame
frequency on duty cycle is listed in table 31.
LCD duty cycle/clock control register (LMR: $01C)
Bit
Initial value
Read/Write
Bit name
3
0
W
LMR3
2
0
W
LMR2
1
0
W
LMR1
0
0
W
LMR0
LMR3
0
LMR2 Input clock source selection
0 ^{CL0 (32.768-kHz × duty/64: when}
32.768-kHz oscillation is used)
0
1 CL1 (f_OSC × duty cycle/1024)
1
0 CL2 (fOSC × duty cycle/8192)
1
1 CL3 (refer to table 31)
LMR1
0
0
1
1
LMR0
0
1
0
1
Duty cycle selection
1/4 duty
1/3 duty
1/2 duty
Static
Figure 97 LCD Duty-Cycle/Clock Control Register (LMR)
107