HD404629R Datasheet, PDF (17/157 Pages) Renesas Technology Corp – AS Microcomputer Incorporating a DTMF Generator Circuit

HD404629R Series
Memory Register (MR) Area ($040–$04F): Consisting of 16 addresses, this area (MR0–MR15) can be
accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6.
Memory registers
$040 MR(0)
$041
$042
$043
$044
$045
$046
$047
$048
$049
$04A
$04B
$04C
$04D
$04E
$04F
MR(1)
MR(2)
MR(3)
MR(4)
MR(5)
MR(6)
MR(7)
MR(8)
MR(9)
MR(10)
MR(11)
MR(12)
MR(13)
MR(14)
MR(15)
$3C0
$3FF
Stack area
Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1
PC₁₃–PC₀ : Program counter
ST: Status flag
CA: Carry flag
Bit 3
$3FC ST
$3FD PC₁₀
$3FE CA
$3FF PC₃
Bit 2
PC₁₃
PC₉
PC₆
PC₂
Bit 1
PC₁₂
PC₈
PC₅
PC₁
Bit 0
PC₁₁
PC₇
PC₄
PC₀
Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position
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