HD404629R Datasheet, PDF (46/157 Pages) Renesas Technology Corp – AS Microcomputer Incorporating a DTMF Generator Circuit

HD404629R Series
Internal Oscillator Circuit
A block diagram of the clock generation circuit is shown in figure 26. As shown in table 22, a ceramic
oscillator can be connected to OSC₁ and OSC₂, and a 32.768-kHz oscillator can be connected to X1 and
X2. The system oscillator can also be operated by an external clock. Bit 0 and 1 (SSR1) of the system
clock select register (SSR: $029) must be set according to the frequency of the oscillator connected to
OSC₁ and OSC₂ (figure 27).
Note: If the system clock select register (SSR: $029) setting does not match the oscillator frequency,
DTMF generator and subsystems using the 32.768-kHz oscillation will malfunction.
OSC₂
OSC₁
X1
X2
LSON
System ^fOSC 1/4
f_cyc
clock
oscillator
division
circuit
t_cyc
Timing
generation
circuit
Sub-
system
f_X
f_SUB
1/8 or 1/4
Timing
division ^tsubcyc generator
clock
circuit*
circuit
oscillator
ø_CPU
System
clock
selection
circuit
ø_PER
CPU with ROM,
RAM, registers,
flags, and I/O
Internal
Peripheral
module
interrupts
(other than timer A)
TMA3 bit
1/8
division
circuit
f_W
t_Wcyc
Timing
generation
circuit
Clock
Time-base
clock øCLK
selection
circuit
Timer A
interrupt
Note: * 1/8 or 1/4 division ratio can be selected by setting bit 2 of the system
clock select register (SSR: $029).
Figure 26 Clock Generation Circuit
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