HD404629R Datasheet, PDF (87/157 Pages) Renesas Technology Corp – AS Microcomputer Incorporating a DTMF Generator Circuit

Table 29 Serial Transmit Clock (Prescaler Output)
SMRB
Bit 0
0
Bit 2
0
1
1
0
1
SMRA
Bit 1
0
1
0
0
1
0
Bit 0
0
1
0
1
0
1
0
1
0
1
0
1
Prescaler Division Ratio
÷ 2048
÷ 512
÷ 128
÷ 32
÷8
÷2
÷ 4096
÷ 1024
÷ 256
÷ 64
÷ 16
÷4
HD404629R Series
Transmit Clock Frequency
4096t_cyc
1024t_cyc
256t_cyc
64t_cyc
16t_cyc
4t_cyc
8192t_cyc
2048t_cyc
512t_cyc
128t_cyc
32t_cyc
8t_cyc
Operating States: The serial interface has the following operating states; transitions between them are
shown in figure 71.
 STS wait state
 Transmit clock wait state
 Transfer state
 Continuous clock output state (only in internal clock mode)
• STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 71). In STS
wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is
then executed (01, 11), the serial interface enters transmit clock wait state.
• Transmit clock wait state: Transmit clock wait state is between the STS execution and the falling edge
of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments
the octal counter, shifts the serial data register, and enters the serial interface in transfer state. However,
note that if continuous clock output mode is selected in internal clock mode, the serial interface does not
enter transfer state but enters continuous clock output state (17).
The serial interface enters STS wait state by writing data to serial mode register A (SMRA: $005) (04,
14) in transmit clock wait state.
• Transfer state: Transfer state is between the falling edge of the first clock and the rising edge of the
eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the
octal counter to 000, and the serial interface enters another state. When the STS instruction is executed
(05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is
entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In
internal clock mode, the transmit clock stops after outputting eight clocks.
85