HD404629R Datasheet, PDF (47/157 Pages) Renesas Technology Corp – AS Microcomputer Incorporating a DTMF Generator Circuit

HD404629R Series
System clock select register (SSR: $029)
Bit
Initial value
Read/Write
Bit name
3
0
W
SSR3
2
0
W
SSR2
1
0
W
SSR1
0
0
W
SSR0
SSR3 32-kHz oscillation stop
SSR1 SSR0 System clock selection
0
Oscillation operates in stop mode
0
0
400 kHz
1
Oscillation stops in stop mode
0
1
800 kHz
32-kHz oscillation division
SSR2 ratio selection
1
0
2 MHz
1
1
4 MHz
0
f_SUB = f_X/8
1
f_SUB = f_X/4
Note: SSR3 is cleared only by a RESET input. SSR3 will not be cleared by a STOPC input during
stop mode, and will retain its value.
SSR3 will also not be cleared upon entering stop mode.
Figure 27 System Clock Select Register (SSR)
D₀
GND
X2
X1
RESET
OSC₂
OSC₁
TEST
AV_SS
GND
Figure 28 Typical Layouts of Crystal and Ceramic Oscillator
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