455A Datasheet, PDF (84/148 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

455A Group
INSTRUCTIONS
Each instruction is described as follows;
1. Index list of instruction function
2. Machine instructions (index by alphabet)
3. Machine instructions (index by function)
4. Instruction code table
SYMBOL
The symbols shown below are used in the following list of
instruction function and the machine instructions.
Symbol
Contents
Symbol
Contents
A
Register A (4 bits)
R2H
Timer 2 reload register (8 bits)
B
Register B (4 bits)
RLC
Timer LC reload register (4 bits)
DR
Register DR (3 bits)
PS
Prescaler
E
Register E (8 bits)
T1
Timer 1
V1
Interrupt control register V1 (4 bits)
T2
Timer 2
V2
Interrupt control register V2 (4 bits)
TLC
Timer LC
I1
Interrupt control register I1 (4 bits)
T1F
Timer 1 interrupt request flag
PA
Timer control register PA (1 bit)
T2F
Timer 2 interrupt request flag
W1
Timer control register W1 (4 bits)
T3F
Timer 3 interrupt request flag
W2
Timer control register W2 (4 bits)
WDF1
Watchdog timer flag
W3
Timer control register W3 (4 bits)
WEF
Watchdog timer enable flag
W4
Timer control register W4 (4 bits)
INTE
Interrupt enable flag
W5
Timer control register W5 (5 bits)
EXF0
External 0 interrupt request flag
MR
Clock control register MR (4 bits)
VDF
Voltage drop detection circuit flag
RG
Clock control register RG (3 bits)
P
Power down flag
L1
LCD control register L1 (4 bits)
D
Port D (8 bits)
L2
LCD control register L2 (4 bits)
P0
Port P0 (4 bits)
L3
LCD control register L3 (4 bits)
P1
Port P1 (4 bits)
C1
LCD control register C1 (4 bits)
P2
Port P2 (4 bits)
C2
LCD control register C2 (4 bits)
P3
Port P3 (4 bits)
C3
LCD control register C3 (4 bits)
C
Port C (1 bit)
K0
Key-on wakeup control register K0 (4 bits)
INT
INT pin (1 bit)
K1
Key-on wakeup control register K1 (4 bits)
K2
Key-on wakeup control register K2 (4 bits)
x
Hexadecimal variable
K3
Key-on wakeup control register K3 (4 bits)
y
Hexadecimal variable
PU0
Pull-up control register PU0 (4 bits)
z
Hexadecimal variable
PU1
Pull-up control register PU1 (4 bits)
p
Hexadecimal variable
PU2
Pull-up control register PU2 (4 bits)
n
Hexadecimal constant
PU3
Pull-up control register PU3 (4 bits)
i
Hexadecimal constant
FR0
Port output structure control register FR0 (4 bits)
j
Hexadecimal constant
FR1
Port output structure control register FR1 (4 bits) A3 A2 A1 A0 Binary notation of hexadecimal variable A
FR2
Port output structure control register FR2 (4 bits)
(same for others)
FR3
Port output structure control register FR3 (4 bits) ←
Direction of data movement
X
Register X (4 bits)
()
Contents of registers and memories
Y
Register Y (4 bits)
−
Negate, Flag unchanged after executing instruction
Z
Register Z (2 bits)
M (DP)
RAM address pointed by the data pointer
DP
Data pointer (10 bits)
(It consists of registers X, Y, and Z)
PC
Program counter (14 bits)
a
Label indicating address a6 a5 a4 a3 a2 a1 a0
p, a
Label indicating address a6 a5 a4 a3 a2 a1 a0 in page
p6 p5 p4 p3 p2 p1 p0
PCH
High-order 7 bits of program counter
PCL
Low-order 7 bits of program counter
C+x
Hex. C + Hex. number x (also same for others)
SK
Stack register (14 bits × 8)
?
Decision of state shown before “?”
SP
Stack pointer (3 bits)
←→
Data exchange between a register and memory
CY
Carry flag
UPTF
High-order bit reference enable flag
RPS
Prescaler reload register (8 bits)
R1
Timer 1 reload register (8 bits)
R2L
Timer 2 reload register (8 bits)
Note 1. The 455A Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased
by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if
the TABP p, RT, or RTS instruction is skipped.
Rev.1.01 Feb 15, 2008 Page 84 of 146
REJ03B0224-0101