|
455A Datasheet, PDF (8/148 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER | |||
|
◁ |
455A Group
DEFINITION OF CLOCK AND CYCLE
⢠Operation source clock
The operation source clock is the source clock to operate this
product. In this product, the following clocks are used.
⢠Clock (f(XIN)) by the external ceramic resonator
⢠Clock (f(XIN)) by the external input
⢠Clock (f(HSOCO)) of the high-speed on-chip oscillator which is
the internal oscillator
⢠Clock (f(XCIN)) by the external quartz-crystal oscillation
⢠Clock (f(LSOCO)) by the low-speed on-chip oscillator
⢠System clock (STCK)
The system clock is the basic clock for controlling this product.
The system clock is selected by the clock control register MR
shown as the table below.
⢠Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
⢠Instruction clock (INSTCK)
The instruction clock is the basic clock for controlling CPU. The
instruction clock (INSTCK) is a signal derived by dividing the
system clock (STCK) by 3. The one instruction clock cycle
generates the one machine cycle.
Table 7 Table Selection of system clock
MR3
Register MR
MR2
MR1
MR0
System clock
1
1
0
0
f(STCK) = f(HSOCO)/8
1
0
0
0
f(STCK) = f(HSOCO)/4
0
1
0
0
f(STCK) = f(HSOCO)/2
0
0
0
0
f(STCK) = f(HSOCO)
1
1
0
1
f(STCK) = f(XIN)/8
1
0
0
1
f(STCK) = f(XIN)/4
0
1
0
1
f(STCK) = f(XIN)/2
0
0
0
1
f(STCK) = f(XIN)
1
1
1
0
f(STCK) = f(XCIN)/8
1
0
1
0
f(STCK) = f(XCIN)/4
0
1
1
0
f(STCK) = f(XCIN)/2
0
0
1
0
f(STCK) = f(XCIN)
1
1
1
1
f(STCK) = f(LSOCO)/8
1
0
1
1
f(STCK) = f(LSOCO)/4
0
1
1
1
f(STCK) = f(LSOCO)/2
0
0
1
1
f(STCK) = f(LSOCO)
Note 1. The f(HSOCO)/8 is selected after system is released from reset
Operation mode
Internal frequency divided by 8 mode
Internal frequency divided by 4 mode
Internal frequency divided by 2 mode
Internal frequency through mode
High-speed frequency divided by 8 mode
High-speed frequency divided by 4 mode
High-speed frequency divided by 2 mode
High-speed through mode
Low-speed frequency divided by 8 mode
Low-speed frequency divided by 4 mode
Low-speed frequency divided by 2 mode
Low-speed through mode
Internal Low-speed frequency divided by 8 mode
Internal Low-speed frequency divided by 4 mode
Internal Low-speed frequency divided by 2 mode
Internal Low-speed through mode
Rev.1.01 Feb 15, 2008 Page 8 of 146
REJ03B0224-0101
|
▷ |