455A Datasheet, PDF (45/148 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

455A Group
(2) LCD clock control
The LCD clock is determined by the timer LC setting value and
timer LC count source.
After setting data to timer LC, timer LC starts counting by setting
count source with bit 2 of register W4 and setting bit 3 of register
W4 to “1.”
Accordingly, the frequency (F) of the LCD clock is obtained by
the following formula. Numbers ((1) to (3)) shown below the
formula correspond to numbers in Figure 44, respectively.
• When using the system clock (STCK) as timer LC count
source (W42=“1”)
F = STCK × ¹ × ¹
LC + 1
2
(1)
(2)
(3)
[LC: 0 to 15]
• When using the bit 4 of timer 3 as timer LC count source
(W42=“0”)
F = T34 × ¹ × ¹
LC + 1 2
(1)
(2)
(3)
[LC: 0 to 15]
The frame frequency and frame period for each display method
can be obtained by the following formula:
F
Frame frequency =
(Hz)
n
n
Frame frequency =
F
(Hz)
F: LCD clock frequency
1/n: Duty
T34
STCK
(1)
W42
0
1
W43
(2)
Timer LC (4)
Reload register RLC (4)
(TLCA)
(TLCA)
Register A
Fig 44. LCD clock control circuit structure
(3) LCD RAM
RAM contains areas corresponding to the liquid crystal display.
When “1” is written to this LCD RAM, the display pixel
corresponding to the bit is automatically displayed.
(3)
1/2
LCD clock
Z
1
X
12
13
14
15
Y
bit ₃
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
8
SEG0 SEG0 SEG0 SEG0 SEG8 SEG8 SEG8 SEG8 SEG16 SEG16 SEG16 SEG16 SEG24 SEG24 SEG24 SEG24
9
SEG1 SEG1 SEG1 SEG1 SEG9 SEG9 SEG9 SEG9 SEG17 SEG17 SEG17 SEG17 SEG25 SEG25 SEG25 SEG25
10
SEG2 SEG2 SEG2 SEG2 SEG10 SEG10 SEG10 SEG10 SEG18 SEG18 SEG18 SEG18 SEG26 SEG26 SEG26 SEG26
11
SEG3 SEG3 SEG3 SEG3 SEG11 SEG11 SEG11 SEG11 SEG19 SEG19 SEG19 SEG19 SEG27 SEG27 SEG27 SEG27
12
SEG4 SEG4 SEG4 SEG4 SEG12 SEG12 SEG12 SEG12 SEG20 SEG20 SEG20 SEG20 SEG28 SEG28 SEG28 SEG28
13
SEG5 SEG5 SEG5 SEG5 SEG13 SEG13 SEG13 SEG13 SEG21 SEG21 SEG21 SEG21 SEG29 SEG29 SEG29 SEG29
14
SEG6 SEG6 SEG6 SEG6 SEG14 SEG14 SEG14 SEG14 SEG22 SEG22 SEG22 SEG22 SEG30 SEG30 SEG30 SEG30
15
COM
SEG7 SEG7 SEG7 SEG7 SEG15 SEG15 SEG15 SEG15 SEG23 SEG23 SEG23 SEG23 SEG31 SEG31 SEG31 SEG31
COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
Fig 45. LCD RAM map
Rev.1.01 Feb 15, 2008 Page 45 of 146
REJ03B0224-0101