455A Datasheet, PDF (78/148 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

455A Group
Timer control register PA
PA0 Prescaler control bit
at reset : 02
0 Stop (state retained)
1 Operating
at power down : 02
W
TAPP
Timer control register W1
at reset : 00002
at power down : state retained
W13
Timer 1 count auto-stop circuit selection bit
(Note 2)
0 Timer 1 count auto-stop circuit not selected
1 Timer 1 count auto-stop circuit selected
W12 Timer 1 control bit
0 Stop (state retained)
1 Operating
W11 W10
Count source
W11
0 0 PWM signal (PWMOUT)
Timer 1 count source selection bits (Note 3) 0 1 Prescaler output (ORCLK)
1 0 Timer 3 underflow signal (T3UDF)
W10
1 1 CNTR input
R/W (Note 1)
TAW1/TW1A
Timer control register W2
W23 CNTR pin function control bit
W22
PWM signal
“H” interval expansion function control bit
W21 Timer 2 control bit
W20 Timer 2 count source selection bit
at reset : 00002
at power down : 00002
0 CNTR pin output invalid
1 CNTR pin output valid
0 PWM signal “H” interval expansion function invalid
1 PWM signal “H” interval expansion function valid
0 Stop (state retained)
1 Operating
0 XIN input
1 Prescaler output (ORCLK)/2
R/W
TAW2/TW2A
Timer control register W3
W33 Timer 3 control bit
W32
W31
Timer 3 count value selection bits
W30
at reset : 00002
at power down : state retained
0 Stop (initial state)
1 Operating
W32 W31 W30
Count value
000
Underflow every 512 count
001
Underflow every 1024 count
010
Underflow every 2048 count
011
Underflow every 4096 count
100
Underflow every 8192 count
101
Underflow every 16384 count
110
Underflow every 32768 count
111
Underflow every 65536 count
R/W
TAW3/TW3A
Timer control register W4
at reset : 00002
at power down : state retained
W43 Timer LC control bit
0 Stop (state retained)
1 Operating
W42 Timer LC count source selection bit
0 Bit 4 (T34) of timer 3
1 System clock (STCK)
W41
CNTR pin output auto-control circuit
selection bit
0 CNTR output auto-control circuit not selected
1 CNTR output auto-control circuit selected
W40 CNTR pin input count edge selection bit
0 Falling edge
1 Rising edge
Note 1. “R” represents read enabled, and “W” represents write enabled.
Note 2. This function is valid only when the timer 1 count start synchronous circuit is selected (I10 =“1”).
Note 3. Port C output is invalid when CNTR input is selected for the timer 1 count source.
R/W
TAW4/TW4A
Rev.1.01 Feb 15, 2008 Page 78 of 146
REJ03B0224-0101