455A Datasheet, PDF (71/148 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

455A Group
(11)Prescaler
Stop prescaler counting and then execute the TABPS instruction
to read its data.
Stop prescaler counting and then execute the TPSAB instruction
to write data to prescaler.
(12)Timer count source
Stop timer 1, 2 or LC counting to change its count source.
(13)Reading the count value
Stop timer 1 or 2 counting and then execute the TAB1 or TAB2
instruction to read its data.
(18)Prescaler, timer 1 count start timing and count time
when operation starts
Count starts from the first rising edge of the count source (2) in
Figure 69 after prescaler and timer operations start (1) in Figure
69.
Time to first underflow (3) in Figure 69 is shorter (for up to 1
period of the count source) than time among next underflow (4)
in Figure 69 by the timing to start the timer and count source
operations after count starts.
When selecting CNTR input as the count source of timer 1, timer
1 operates synchronizing with the count edge (falling edge or
rising edge) of CNTR input selected by software.
(14)Writing to the timer
Stop timer 1, 2 or LC counting and then execute the T1AB,
T2AB, T2R2L or TLCA instruction to write data to timer.
(15)Writing to reload register
In order to write a data to the reload register R1 while the timer 1
is operating, execute the TR1AB instruction except a timing of
the timer 1 underflow.
In order to write a data to the reload register R2H while the timer
2 is operating, execute the T3HAB instruction except a timing of
the timer 2 underflow.
(16)PWM signal
If the timer 2 count stop timing and the timer 2 underflow timing
overlap during output of the PWM signal, a hazard may occur in
the PWM output waveform.
When “H” interval expansion function of the PWM signal is
used, set “1” or more to reload register R2H.
Set the port C output latch to “0” to output the PWM signal from
C/CNTR pin.
(17)Timer 3
Stop timer 3 counting to change its count source.
When operating timer 3 during clock operating mode, set 1 cycle
or more of count source to the following period; from setting bit
3 of register W3 to “1” till executing the POF instruction.
(2)
Count source
Count source
(When falling edge of
CNTR input is selected)
Timer 1 value 3 2 1 0 3 2 1 0 3 2
Timer 1 underflow signal
(3)
(4)
(1) Timer start
Fig 69. Timer count start timing and count time when
operation starts (1)
(19)Timer 2, LC count start timing and count time when
operation starts
Count starts from the first edge of the count source (2) in Figure
70 after timer 2 and LC operation start (1) in Figure 70.
Time to first underflow (3) in Figure 70 is different (for up to 1
period of the count source) from time among next underflow (4)
in Figure 70 by the timing to start the timer and count source
operations after count starts.
(2)
Count source
Timer value
3
210321032
Timer underflow signal
(3)
(4)
(1) Timer start
Fig 70. Timer count start timing and count time when
operation starts (2)
Rev.1.01 Feb 15, 2008 Page 71 of 146
REJ03B0224-0101