455A Datasheet, PDF (77/148 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

455A Group
Clock control register MR
MR3
Operation mode selection bits
MR2
MR1
System clock selection bits (Note 2)
MR0
at reset : 11002
at power down : state retained
MR3 MR2
Operation mode
0 0 Through mode
0 1 Frequency divided by 2 mode
1 0 Frequency divided by 4 mode
1 1 Frequency divided by 8 mode
MR1 MR0
System clock
0 0 f(HSOCO)
0 1 f(XIN)
1 0 f(XCIN)
1 1 f(LSOCO)
R/W
TAMR/TMRA
Clock control register RG
at reset : 10002
at power down : state retained
W
TRGA
RG
Low-speed on-chip oscillator (f(LSOCO))
control bit (Note 3)
0 Low-speed on-chip oscillator (f(LSOCO)) oscillation available
1 Low-speed on-chip oscillator (f(LSOCO)) oscillation stop
RG2 Sub-clock (f(XCIN)) control bit (Note 3)
0 Sub-clock (f(XCIN)) oscillation available, ports D6 and D7 not selected
1 Sub-clock (f(XCIN)) oscillation stop, ports D6 and D7 selected
RG1 Main-clock (f(XIN)) control bit (Note 3)
0 Main clock (f(XIN)) oscillation available
1 Main clock (f(XIN)) oscillation stop
RG0
High-speed on-chip oscillator (f(HSOCO))
control bit (Note 3)
0 High-speed on-chip oscillator (f(HSOCO)) oscillation available
1 High-speed on-chip oscillator (f(HSOCO)) oscillation stop
Note 1. R” represents read enabled, and “W” represents write enabled.
Note 2. The stopped clock cannot be selected for system clock.
Note 3. The oscillation circuit selected for system clock cannot be stopped.
Rev.1.01 Feb 15, 2008 Page 77 of 146
REJ03B0224-0101