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455A Datasheet, PDF (105/148 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER | |||
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455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAB2 (Transfer data to Accumulator and register B from timer 2)
Instruc-
Number of
tion
code
D9
D0
1 0 0 1 1 1 0 0 0 1 2 2 7 1 16
words
1
Number of
cycles
1
Flag CY
-
Skip condition
-
Opera- (B) â (T27âT24)
tion: (A) â (T23âT20)
Grouping: Timer operation
Description: Transfers the high-order 4 bits (T27âT24) of timer 2 to reg-
ister B.
Transfers the low-order 4 bits (T23âT20) of timer 2 to regis-
ter A.
TABE (Transfer data to Accumulator and register B from register E)
Instruc-
Number of
tion
code
D9
D0
0 0 0 0 1 0 1 0 1 0 2 0 2 A 16
words
1
Number of
cycles
1
Flag CY
-
Skip condition
-
Opera- (B) â (E7âE4)
tion: (A) â (E3âE0)
Grouping: Register to register transfer
Description: Transfers the high-order 4 bits (E7âE4) of register E to reg-
ister B, and low-order 4 bits of register E to register A.
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
Instruc-
tion
D9
D0
code
0
0
1
0 p5 p4 p3 p2 p1 p0 2
0
8
+p
p
16
Number of
words
1
Number of
cycles
3
Flag CY
-
Skip condition
-
Opera-
tion:
(SP) â (SP) + 1
(SK(SP)) â (PC)
(PCH) â p
(PCL) â (DR2âDR0, A3âA0)
(B) â (ROM(PC))7â4
(A) â (ROM(PC))3â0
(UPTF) â 1
(DR1, DR0) â (ROM(PC))9, 8
(DR2) â 0
(PC) â (SK(SP))
(SP) â (SP) â 1
Grouping: Arithmetic operation
Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to
0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by
registers A and D in page p. When UPTF is 1, Transfers bits 9, 8 to the low-
order 2 bits (DR1, DR0) of register D, and â0â is stored to the least significant
bit (DR2) of register D.
When this instruction is executed, 1 stage of stack register (SK) is used.
Note:
p is 0 to 63 for M3455AG8, and p is 0 to 95 for M3455AGC.
When this instruction is executed, be careful not to over the stack because 1
stage of stack register is used.
TABPS (Transfer data to Accumulator and register B from Pre-Scaler)
Instruc-
tion
D9
D0
code
1 0 0 1 1 1 0 1 0 1 2 2 7 5 16
Number of
words
1
Number of
cycles
1
Flag CY
-
Skip condition
-
Opera- (B) â (TPS7âTPS4)
tion: (A) â (TPS3âTPS0)
Grouping: Timer operation
Description: Transfers the high-order 4 bits of prescaler to register B.
Transfers the low-order 4 bits of prescaler to register A.
Rev.1.01 Feb 15, 2008 Page 105 of 146
REJ03B0224-0101
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