455A Datasheet, PDF (50/148 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

455A Group
RESET FUNCTION
System reset is performed by the followings:
• “L” level is applied to the RESET pin externally,
• System reset instruction (SRST) is executed,
• Reset occurs by watchdog timer,
• Reset occurs by built-in power-on reset
• Reset occurs by voltage drop detection circuit
Then when “H” level is applied to RESET pin, software starts
from address 0 in page 0.
(Note 1)
RESET pin
(Note 2)
(Note 1)
Pull-up transistor
Voltage drop
detection circuit
Internal reset signal
Power-on reset circuit
SRST instruction
Watchdog reset signal
WEF
Notes 1:
This symbol represents a parasitic diode.
2: Applied potential to RESET pin must be VDD or less.
Fig 48. Structure of RESET pin and its peripherals
Table 21 Port state at reset
Name
Function
D0−D4
D0−D4
D5/INT
D5
XCIN/D6, XCOUT/D7
XCIN, XCOUT
P00/SEG16−P03/SEG19
P00−P03
P10/SEG20−P13/SEG23
P10−P13
P20/SEG24−P23/SEG27
P20−P23
P30/SEG28−P33/SEG31
P30−P33
SEG0/VLC3−SEG2/VLC1
SEG0−SEG2
SEG3−SEG15
SEG3−SEG15
COM0−COM3
COM0−COM3
C/CNTR
C/CNTR
Note 1. Output latch is set to “1.”
Note 2. The output structure is N-channel open-drain.
Note 3. Pull-up transistor is turned OFF.
State
High-impedance (Notes 1, 2)
High-impedance (Notes 1, 2)
Sub-clock input
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
VLC3 (VDD) level
VLC3 (VDD) level
VLC3 (VDD) level
“L” (VSS) level
Rev.1.01 Feb 15, 2008 Page 50 of 146
REJ03B0224-0101