455A Datasheet, PDF (33/148 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

455A Group
XCIN
ORCLK
Low-speed
High-speed
W51, W50
00
01
W33
Timer3 (16)
1 - - 4 - - - - - 9 10 11 12 13 14 15 16
W32 W31
111
110
101
100
011
010
001
000
W30
T3F
W42
0
Timer LC (4)
1/2
1
W43
Reload register RLC (4)
(TLCA)
(TLCA)
Register A
Timer 3
interrupt
Timer 3 underflow signal
(T3UDF)
LCD clock
INSTCK
Watchdog timer (16)
1 - - - - - - - - - - - - - 16
(Note 1)
SQ
WDF1
WRST
instruction
Reset signal
(Note 3)
R
SQ
WEF
DWDT instruction _R
+
(Note 2)
WRST instruction
Data is set automatically from each reload register
when timer underflows (auto-reload function).
DQ
Watchdog reset
signal
T R ^{reset signal}
Note 1: Flag WDF1 is cleared to “0” and the next instruction is skipped when the WRST instruction is executed
while flag WDF1 = “1”.
The WRST instruction is equivalent to the NOP instruction while flag WDF1 = “0”.
2: Flag WEF is cleared to “0” and watchdog timer reset does not occur when the DWDT instruction and
WRST instruction are executed continuously.
3: The WEF flag is set to “1” at system reset or RAM back-up mode.
Fig 34. Timers structure (2)
Rev.1.01 Feb 15, 2008 Page 33 of 146
REJ03B0224-0101